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Xilinx公司Accel DSP项目
xilinx accel dsp实例项目工程-xilinx accel dsp project
- 2023-03-09 20:10:02下载
- 积分：1
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File name: ADC0809.vhd features: Based on the VHDL language, easy to control imp...
文件名：ADC0809.vhd功能：基于VHDL语言，实现对ADC0809简单控制说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟号，这里由FPGA的系统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。-File name: ADC0809.vhd features: Based on the VHDL language, easy to control implementation of the ADC0809 Description: ADC0809 internal clock does not need external 10KHz ~ 1290Hz clock number, here by the FPGA system clock (50MHz) frequency by 256 points to be clk1 (195KHz ) as the conversion ADC0809 clock job.
- 2023-07-04 18:20:03下载
- 积分：1
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shuzijishiqi
基于VHDL的数字计时器，手动可控正计时和倒计时(含复位键和使能键)(VHDL-based digital timer and countdown timer being controlled manually (with the reset button and enable key))
- 2016-12-05 19:57:07下载
- 积分：1
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mac_layer_switch_latest.tar
source code for Ethernet logic
- 2017-04-05 08:04:27下载
- 积分：1
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Cadence VHDL Operational the package, seeking to achieve root, You are not squar...
Cadence的VHDL运算库包，实现求方根，平方你是不是以前不知道怎么弄．哈哈．-Cadence VHDL Operational the package, seeking to achieve root, You are not square did not know how get. Ha ha.
- 2022-08-16 03:35:39下载
- 积分：1
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sample_wave
可以产生8比特的采样波形，非常不错的VHDL程序(Sampling can produce 8-bit waveform, very good VHDL program)
- 2010-10-12 20:03:07下载
- 积分：1
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CORDIC算法的FFT实现
本代码实现了 ； ；CORDIC ； 算法语言；
- 2022-09-09 16:25:03下载
- 积分：1
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McBSP
CPLD对mcbsp的收发操作，占用资源很少(CPLD to mcbsp transceiver operation, small footprint)
- 2011-09-14 16:19:51下载
- 积分：1
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ccd
自己写的一个tcd1209d的时序驱动代码，是用verilog语言编写的，可以借鉴(Of write a tcd1209d of timing-driven code, Verilog language, can learn from)
- 2021-04-08 09:39:00下载
- 积分：1
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dds32_1
说明： 频率合成器实例模块设计。频率分辨率为32位DDS的VHDL程序(Frequency synthesizer module design example. 32-bit DDS frequency resolution of the VHDL program)
- 2011-04-14 13:45:22下载
- 积分：1
