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Chebyshev-filter
利用matlab设计了一个切比雪夫滤波器，并且对滤波器性能进行了仿真分析。(Using the matlab design a chebyshev filter, and has carried on the simulation analysis on filter performance.
)
- 2013-09-05 20:04:36下载
- 积分：1
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SAR-ADC
Complete Successive approximation Analog to digital converter along with the source code
- 2013-04-21 23:42:03下载
- 积分：1
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一个以太网卡的硬件描述，可以参考进行设计网卡芯片。
一个以太网卡的硬件描述，可以参考进行设计网卡芯片。-an Ethernet card hardware description, reference card chip design.
- 2023-08-18 05:00:03下载
- 积分：1
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Multiplier
圖形介面乘法器,也可自行使用verilog去改(Graphical interface multiplier, also free to use verilog go and change)
- 2012-10-25 21:12:49下载
- 积分：1
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EDA
计数器的程序，eda编程用的，vhdl语言编程，大家下载看看吧(Program counter, eda programming used, vhdl programming
)
- 2010-12-22 20:47:02下载
- 积分：1
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DE2
DE2-70,NIOS reference file,
- 2022-02-01 13:58:03下载
- 积分：1
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mif
使用metlab生产正弦波和三角波的采样值，供vhdl等语言调用来产生波形(use metlab production sine wave and triangular wave of sampling, for languages such as call vhdl to generate waveforms)
- 2007-05-15 15:51:39下载
- 积分：1
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FPGA锁相环实验
说明： FPGA锁相环实验：
顶层文件加底层IP文件构成
top中例化ip核pll(Experiment of Phase-Locked Loop Based on FPGA)
- 2020-06-22 04:00:01下载
- 积分：1
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Verilog HDL语言编写的5分频电路。采用两路时钟相逻辑作用产生。...
Verilog HDL语言编写的5分频电路。采用两路时钟相逻辑作用产生。-Verilog HDL prepared by the five-frequency circuits. Clock using two phase logic role.
- 2022-03-28 17:01:44下载
- 积分：1
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DVI_LED
基于DVI协议动态全彩LED大屏幕发送卡设计与实现,成本比较低,效果很好,可以实现高清视频(Dynamic full-color LED large screen based on the DVI protocol send a card design and relatively low cost, good effect, and can achieve high-definition video)
- 2012-08-03 13:08:44下载
- 积分：1
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