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基于fpga的多功能数字时钟的实现，已经编译过了，绝对可行
基于fpga的多功能数字时钟的实现，已经编译过了，绝对可行-fpga-baseed clock
- 2022-02-04 17:16:32下载
- 积分：1
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CCPRRIzipP
一种基于CPRI标准的WCDMA NoddeB射频光纤拉远接口FPGA设计.pdf
(CPRI compliant the WCDMA NoddeB RF fiber pull far from the interface of the FPGA design. Pdf)
- 2012-07-19 22:29:39下载
- 积分：1
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veilog code user can derict use it for the base mode.
veilog 代码 用户可以直接调用，作为底层模块。同时已经编译成功，可以作为基本单元库。-veilog code user can derict use it for the base mode.
- 2023-08-09 02:40:03下载
- 积分：1
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fsm
有限状态机工作原理、设计方法、步骤等精要说明(Finite state machine working principle, design method, such as Essentials of steps to explain)
- 2010-02-13 17:46:25下载
- 积分：1
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bt656_decode
将嵌入式BT656格式数据解码出带行场同步信号的YCbCr422格式数据(Decoding Embedded BT656 Format Data to YCbCr422 Format Data with Field Synchronization Signa)
- 2021-01-28 10:38:35下载
- 积分：1
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lut_multiplier
使用verliog设计实现LUT查找表乘法器，通过modelsim仿真验证通过(Designed and implemented using the LUT lookup table verliog multipliers, through simulation by modelsim)
- 2021-04-09 10:18:59下载
- 积分：1
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3he11
产生SH,SP,RS,SP,φ1,φ2驱动脉冲，用于驱动TCD1501的的源代码(To generate SH, SP, RS, SP, φ1, φ2 drive pulse for driving TCD1501 source code)
- 2013-05-15 20:50:30下载
- 积分：1
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FRUDH
用VHDL实现频率计，可测量输入脉冲的频率，并进行简单校正(Realize the frequency of use of VHDL in terms of measurable input pulse frequency, and a simple correction)
- 2008-07-07 20:13:30下载
- 积分：1
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test_vhdl
vhdl测试程序，用于初雪者熟悉hdl的具体语法应用。比较简单了。(VHDL test procedure for the First Snow hdl who are familiar with the application of specific syntax. A relatively simple.)
- 2009-01-09 18:25:34下载
- 积分：1
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DDS signal generator, can produce a variety of waveforms, are mysterious wave, t...
DDS信号发生器，能产生多种波形，正玄波，三角波，方波，频率可调，相位可调-DDS signal generator, can produce a variety of waveforms, are mysterious wave, triangle wave, square wave, frequency tunable, phase adjustable
- 2022-11-28 01:05:04下载
- 积分：1
