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xapp1161
多相滤波系统的设计与实现，有MATLAB仿真程序，有sysgen的系统仿真，还有VHDL代码，其中还有FIR的系数参数等等(Polyphase filter system, the design and implementation includes a MATLAB simulation program, sysgen system simulation, and VHDL code, including FIR coefficient parameters, and so on
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- 2021-02-15 17:29:47下载
- 积分：1
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电子密码锁的vhdl编程实现，不知以前有没有人做过的。
电子密码锁的vhdl编程实现，不知以前有没有人做过的。-electronic locks VHDL programming, I wonder if the past is not done.
- 2022-06-19 03:31:21下载
- 积分：1
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DE2
基于DE2的视频电话部分源码，实现了视频图像采集，VGA显示，局域网通讯等功能-DE2-based video telephony part of the source code to achieve the video image capture, VGA display, LAN communications function
- 2022-04-18 21:55:17下载
- 积分：1
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基于单片机与CPLD的 等精度频率计，VHDL语言
基于单片机与CPLD的 等精度频率计，VHDL语言-Based on SCM and CPLD
- 2022-11-25 20:35:03下载
- 积分：1
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6_USB_to_SDHC_Lab
altera max10 USB demo，使用了phy，把开发板配置成U盘模式(altera max10 USB demo，using PHY device，design a U pan)
- 2015-10-22 20:47:49下载
- 积分：1
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This document gives the code for programming a CC2500 transceiver using Altera S...
This document gives the code for programming a CC2500 transceiver using Altera Stratix FPGA. The FPGA and CC2500 are connected through SPI mode with the FPGA as the master and CC2500 as the slave.
- 2022-02-26 15:59:21下载
- 积分：1
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基于SOPC EP2C5开发板的I2C总线的A/D D/A例程
基于SOPC EP2C5开发板的I2C总线的A/D D/A例程-A/D AND D/A routings interfaced with i2c based on sopc ep2c5
- 2022-01-25 22:27:04下载
- 积分：1
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xilinx-timing-constrains
ISE时序约束笔记——Global Timing Constraints，这个文档中详细介绍了如何使用ISE中约束工具和原理，对fpga水平提高有很大帮助(In this file , global timing constraints is introduced very clearly. It can really helps)
- 2012-04-16 11:08:45下载
- 积分：1
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用VHDL编写的4、7、40、64、84计数器，可将程序中的具体数字设成任意值。...
用VHDL编写的4、7、40、64、84计数器，可将程序中的具体数字设成任意值。-Using VHDL written 4,7,40,64,84 counter, you can program specific figures set to any value.
- 2023-02-12 05:30:04下载
- 积分：1
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PN-(2)
伪随机序列FPGA 通过仿真 M3000(Pseudo-random sequence M3000 FPGA simulation)
- 2011-06-09 13:40:00下载
- 积分：1
