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ahb_master_monitor
AHB master monitor for verification
- 2015-04-03 19:38:06下载
- 积分：1
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DDS now to the use of more extensive relative bandwidth, frequency conversion ti...
DDS在现在运用月来越广泛，在相对带宽、频率转换时间、相位连续性、正交输出、高分辨力以及集成化等方面都远远超过了传统频率合成技术所能达到的水平，为系统提供了优于模拟信号源的性能。利用DDS技术可以很方便地实现多种信号。在FPGA上实现的DDS-DDS now to the use of more extensive relative bandwidth, frequency conversion time, phase continuity, quadrature output, high-resolution and integration, and other aspects far more than the traditional frequency synthesizer technology can achieve the level To provide a superior analog signal source performance. DDS technology can be used very easily to a variety of signal. FPGA Implementation of DDS
- 2022-02-12 02:47:38下载
- 积分：1
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this come from alter ,you can look and find it on line about USB
this come from alter ,you can look and find it on line about USB
- 2023-09-06 16:15:03下载
- 积分：1
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Nios_Example_07_SD_35TFT
这是一个nios工程，控制TFT液晶屏的程序。FPGA平台用Verilog HDL语言编写的，MCU软核程序有C语言编写。通过这一个完成的工程，你就会明白SOPC的一些实现方法。(This is a nios engineering, control TFT LCD screen program. The FPGA platform Verilog HDL language preparation with the nuclear program has a soft, MCU written in C language. Through this a complete project, you will understand some of the SOPC methods of realization.
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- 2011-05-24 16:56:27下载
- 积分：1
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24_Timer
说明： 使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)
- 2021-04-27 21:38:44下载
- 积分：1
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costas
载波同步，costas环，基于Verilog的载波同步环(Carrier synchronization, costas ring, based on Verilog carrier synchronization ring
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- 2021-03-05 13:09:31下载
- 积分：1
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vhdl code for multiplexer and detemines how multiplexer works
vhdl code for multiplexer and detemines how multiplexer works
- 2022-02-21 06:20:43下载
- 积分：1
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使用VHDL语言操作LCD1602
这篇是利用VHDL语言控制LCD1602芯片来显示时钟的简单代码。LCD1602顾名思义是一种02*16，即为两行十六列的液晶显示屏，液晶两行，每行可以显示16个字符，但是CGRAM及CGROM里面一共有160个字符，包括阿拉伯数字，英文字母大小写，常用符号及日文。每个字符对应于一个ASCII码值，在液晶显示屏上显示对应的字符时候，只需要将对应的ASCII码写到DDRAM中就好。
- 2022-07-05 01:39:17下载
- 积分：1
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Lossless_Compression_Method_for_Bayer_Image_and_FP
描述Bayer图像无损压缩的一种先进算法及其如何在FPGA上实现(Description Bayer Image is an advanced lossless compression algorithms in the FPGA to achieve and how)
- 2010-08-31 12:24:49下载
- 积分：1
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VHDL implement serial port, it can communicate with pc, it can accept and send m...
用VHDL实现串口 可以实现与pc机的通信 收发 中断都可以 效果比较好-VHDL implement serial port, it can communicate with pc, it can accept and send message, and it can be interrupted.
- 2022-02-11 22:49:32下载
- 积分：1
