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stopwatch
数字秒表的VHDL代码。当设计文件加载到目标器件后,设计的数字秒表从00-00-00开始计秒。,直到按下停止按键(按键开关S2)。数码管停止计秒。按下开始按键(按键开关S1),数码管继续进行计秒。按下复位按键(核心板上复位键)秒表从00-00-00重新开始计秒。(The VHDL code for digital stopwatch. When the design document loaded into the target device, the designed digital stopwatch count the seconds from the 00-00-00. Until you press stop key (key switch S2). Nixie tube stop count seconds. Press the start button (key switch S1), the digital control continue to count seconds. Press the reset button (core panel reset button) to restart the stopwatch count seconds from the 00-00-00.)
- 2010-03-02 17:17:58下载
- 积分:1
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HDL example source code 1/5
tff_a
HDL example source code 1/5
tff_a
- 2023-03-23 10:10:04下载
- 积分:1
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LaurentCPM
Laurent程序,用于CPM信号的调制,接收和分解,译码,以及判断(Laurent procedures for CPM modulation of the signal, and decomposition receiving, decoding, and to determine)
- 2013-08-16 01:32:40下载
- 积分:1
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20190717
说明: uart documentation, july 17, 2019. the document describes the basics of verilog programming and how to implement them on an fpga device
- 2020-06-21 21:40:01下载
- 积分:1
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fpga_pc_software
计算机组成原理课程实验使用软件,Thinpad教学机教学实验软件
实现mips代码到机器代码之间的转换
实现本机和FPGA板的通信,将机器代码送入
可在本机编写代码送入fpga板的sram中,fpga板的cpu会运行(Computer architecture course experiment using software, Thinpad teaching machine teaching experiment software mips code into machine code conversion for communication between the machine and the FPGA board can be fed into the machine code written in native code into the fpga board sram in, fpga board cpu runs)
- 2014-06-15 18:10:11下载
- 积分:1
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AD9826
AD9826中文说明书 ,对于学习AD9826元件有很大的帮助。(AD9826 Discription in Chinese)
- 2015-04-12 14:22:34下载
- 积分:1
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err
在一些系统中,经常用到对触发信号延时一段时
间后,再对某些目标信号进行采集,通常这段延时要求
非常精确,还要做到范围可调,一般这种延时的最小时
间单位小于100ns。如果选用普通微控制器,延时系统的操作界面比较容易实现,但是靠软件延时得到结果的准确性较低。考虑到芯片功能、开发环境以及接口方便等问题,最终选用一片常用的AlteraSVCPLD
EPM7128SLC3411]作为系统的核心控制部分,来实现
信号延时、输人设定、运行显示的功能。应用Veril-
o苦2〕语言,在Altera的Quartus11WebEditio详3〕软件
环境下进行编程仿真,最后烧写芯片进行系统硬件测试
-err
- 2022-03-12 04:01:42下载
- 积分:1
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CfgDDS_9910
dds ad9910配置的verilog hdl程序,模块化设计,输入待配置的数据,字长,启动信号,即可自动产生时序,完成一次配置,模块还有done握手信号,方便用户调用时,反复多次配置。(dds ad9910 configuration verilog hdl program, modular design, the input data to be configured, word length, the start signal, the timing can be automatically generated, complete a configuration, the module has done handshake, user-friendly call, repeatedly configuration .)
- 2015-04-21 22:03:50下载
- 积分:1
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jk
说明: 基于quartus2的jk触发器设计,内含源码和仿真图(Jk flip-flop design based on the quartus2, containing source code and simulation diagram)
- 2011-11-24 10:47:56下载
- 积分:1
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步进电机
此代码是用于旋转一个步进电机所需的方向。
- 2022-10-22 10:05:04下载
- 积分:1