登录
首页 » VHDL » soft for changing Verilog code to c++ code ,c code

soft for changing Verilog code to c++ code ,c code

于 2022-01-24 发布 文件大小:40.92 kB
0 115
下载积分: 2 下载次数: 1

代码说明:

将Verilog代码转换成C++代码的软件,C源代码。-soft for changing Verilog code to c++ code ,c code

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • matrix-keyboard-
    矩阵键盘控制的FPGA,verilog语言实现,包括rtl,ucf,以及testbench的详尽代码(Exhaustive code matrix keyboard control FPGA, Verilog language, including the rtl, ucf, and testbench)
    2021-01-16 22:18:50下载
    积分:1
  • FPGA_Book_cd
    《无线通信FPGA设计》包含的所有例子源码,包括matlab仿真和verilog源码,本书内容还是非常丰富的,涉及无线通信领域各个方面。不过对于一些比较新的技术,其FPGA实现部分过于简略,难以在工程中实用化。(" Wireless FPGA Design" contains all the examples source code, including the matlab simulation and verilog source code, the contents of this book is still very rich, involved in all aspects of the field of wireless communications. But for some relatively new technology, some of its FPGA implementation is too brief, it is difficult in practical engineering.)
    2009-10-26 14:50:33下载
    积分:1
  • 16bit-multiplier
    实现verilog16位乘法器,verilog新手(achieve 16-bit multiplier)
    2021-04-01 21:09:08下载
    积分:1
  • track_version2
    说明:  fpga实现相关滤波算法中的CSK算法,采用仿真的方式验证结果 fpga是xilinx 仿真工具是vivado2018.2 语言是verilog(The CSK algorithm is implemented in FPGA, and the results are verified by simulation FPGA is Xilinx The simulation tool is vivado 2018.2 Language is Verilog)
    2021-04-29 16:08:42下载
    积分:1
  • EDA
    说明:  十进制到十六进制转换的程序。程序要求从键盘取得一个十进制数,然后把该数以十六进制的形式在屏幕上显示出来。(Decimal to hex conversion program. Procedural requirements to obtain a decimal number from the keyboard, and then the hexadecimal number to be displayed on the screen.)
    2011-03-27 16:42:04下载
    积分:1
  • FPGAPVC_3
    基于SDRAM的PCI采集,上位机为VC编写,桥芯片为PLX9054,项目已经做完,上传5个例程,已经验证通过(SDRAM, PCI-based acquisition, PC for VC preparation, bridge chip for PLX9054, the project has been done, upload 5 routines, has been verified by)
    2015-01-07 22:53:10下载
    积分:1
  • 四位十进制频率计的顶层控制模块,用于生成测频需要的复位及控制信号...
    四位十进制频率计的顶层控制模块,用于生成测频需要的复位及控制信号-four decimal frequency of top-level control modules, used to generate the required frequency measurement and control signals reset
    2022-07-22 04:02:23下载
    积分:1
  • MB
    说明:   基于VHDL语言数字秒表设计,在FPGA实验平台下开发(Digital stopwatch design based on VHDL, FPGA experimental platform under development)
    2015-04-21 20:11:14下载
    积分:1
  • ethmac10g
    千兆以太网设计,包括组包解包,可以实现大数据传输功能。(Unpack the gigabit Ethernet is designed, including group package, can realize large data transfer function.)
    2020-09-01 16:48:09下载
    积分:1
  • bt656_decode
    说明:  将嵌入式BT656格式数据解码出带行场同步信号的YCbCr422格式数据(Decoding Embedded BT656 Format Data to YCbCr422 Format Data with Field Synchronization Signa)
    2021-01-28 10:38:35下载
    积分:1
  • 696518资源总数
  • 105885会员总数
  • 31今日下载