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RISC-V-Reader-Chinese-v2p1
说明： RISC-V 芯片设计规范,很有参考价值，开源芯片设计必备参考资料，希望对大家有帮助。(The RISC-V Foundation is chartered to standardize and promote the open RISC-V instruction set architecture)
- 2020-07-01 23:00:02下载
- 积分：1
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verilog源码，可实现两位的加法器，在xillinx foundation 3.1下验证通过...
verilog源码，可实现两位的加法器，在xillinx foundation 3.1下验证通过-verilog source, the two can achieve Adder, In xillinx foundation 3.1 certification through
- 2022-10-11 18:55:03下载
- 积分：1
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ＶＨＤＬ编写的flash控制器源代码.包含testbench。
ＶＨＤＬ编写的flash控制器源代码.包含testbench。-Prepared by flash controller VHDL source code. Contains testbench.
- 2022-03-18 10:11:40下载
- 积分：1
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bubblesort
根据ASMD图设计验证冒泡排序算法。给出设计程序及时序仿真结果，含纸质报告。(According to the ASMD diagram design, verify the bubble sorting algorithm. Give the design procedure and the simulation result in time, including paper report.)
- 2021-05-08 13:28:35下载
- 积分：1
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TimeGen3
能够绘制数字电路的时序图，是fpga工程师时序设计和分析的神器(for digital circuit timming design and analysis)
- 2017-12-27 19:34:23下载
- 积分：1
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Sensor_CMOS
Code to controlling a Image sensor - CMOS(Code to controlling a Image sensor- CMOS)
- 2009-11-13 03:02:36下载
- 积分：1
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用verilong hdl语言编写的数据采样程序，A/D采用的是TLC5260
用verilong hdl语言编写的数据采样程序，A/D采用的是TLC5260-Verilong hdl language used data sampling procedures, A/D using the TLC5260
- 2023-04-01 09:25:04下载
- 积分：1
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jtag
verilog语言编写的jtag（边界扫描模块），初学的时候可以看看(verilog language jtag (boundary scan module), a novice when you can look)
- 2021-04-27 14:38:44下载
- 积分：1
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FPGAPVC_3
基于SDRAM的PCI采集,上位机为VC编写，桥芯片为PLX9054，项目已经做完，上传5个例程，已经验证通过(SDRAM, PCI-based acquisition, PC for VC preparation, bridge chip for PLX9054, the project has been done, upload 5 routines, has been verified by)
- 2015-01-07 22:53:10下载
- 积分：1
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电梯控制器程序设计与仿真的vhdl源代码
电梯控制器程序设计与仿真的vhdl源代码-Elevator controller design and simulation of vhdl source code
- 2022-04-08 14:05:19下载
- 积分：1
