登录
首页 » VHDL » verilog源码,可实现两位的加法器,在xillinx foundation 3.1下验证通过...

verilog源码,可实现两位的加法器,在xillinx foundation 3.1下验证通过...

于 2022-10-11 发布 文件大小:608.89 kB
0 130
下载积分: 2 下载次数: 1

代码说明:

verilog源码,可实现两位的加法器,在xillinx foundation 3.1下验证通过-verilog source, the two can achieve Adder, In xillinx foundation 3.1 certification through

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • Verilog HDL language proficiency of a good cpu code
    veriloghdl语言熟练的一个很好的cpu代码
    2022-10-31 00:00:03下载
    积分:1
  • yinpin_display0925
    实现音频的I2S通信,音频柱的显示,及其噪声的处理等功能(Realization of audio I2S communications, audio column display, and its noise processing, and other functions)
    2016-01-07 10:08:31下载
    积分:1
  • verilog ADPLL file with testbench
    verilog ADPLL file with testbench
    2022-04-20 22:45:21下载
    积分:1
  • QuartusII brochure+ Chinese version of the manual is aimed at readers of Quartus...
    QuartusII简介手册+中文版 本手册针对的读者是 Quartus II 软件的初学者,它概述了可编程逻辑设计中 Quartus II 软件的功能。 不过,本手册并不是 Quartus II 软件的详尽参考手 册。 相反,本手册只是一本指导书,它解释软件的功能以及显示这些功能如 何帮助您进行 FPGA 和 CPLD 设计。-QuartusII brochure+ Chinese version of the manual is aimed at readers of Quartus II software for beginners, it provides an overview of programmable logic design in Quartus II software. However, this manual is not the Quartus II software, a detailed reference manual. Instead, this manual is a guide book, which explained the functions of the software and show how these features help you to FPGA and CPLD design.
    2022-07-12 19:32:51下载
    积分:1
  • 数字信号处理的FPGA实现(第4版)源码
    说明:  数字信号处理的FPGA实现(第4版)的配套源码,极具参考价值。(The source code of the realization of digital signal processing on FPGA (4th edition) is of great reference value.)
    2021-01-16 23:08:50下载
    积分:1
  • 带LDN的的同步的预置数端子,并且带CLR的异步清零端
    带LDN的的同步的预置数端子,并且带CLR的异步清零端-LDN synchronization with the preset number of terminals, and cleared with CLR Asynchronous client
    2022-02-22 00:30:35下载
    积分:1
  • CH372
    USB设备接口的驱动程序,采用verilogHDL语言编写,并包含相关说明资料(USB device driver interface, using verilogHDL language, and contains descriptive information)
    2014-01-03 02:23:08下载
    积分:1
  • C54x is the Verilog code opencoreip
    c54x的VeriLog程序代码 也是opencoreip-C54x is the Verilog code opencoreip
    2022-03-26 18:08:34下载
    积分:1
  • 01_rtc_ds1302
    说明:  实现基于黑金开发板的实时时钟功能,显示时分秒(Realize the real-time clock function based on black gold development board, display time, minute and second)
    2021-01-11 14:40:12下载
    积分:1
  • 高级加密标准AES的FPGA实现,支持128,256密钥长度格式
    高级加密标准AES的FPGA实现,支持128,256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
    2022-03-25 02:47:08下载
    积分:1
  • 696516资源总数
  • 106783会员总数
  • 25今日下载