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divider
verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。(verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.)
- 2011-08-29 09:12:21下载
- 积分：1
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FPGA
基于FPGA的FFT处理器的实现，适合做fpga的工程技术人员参考-FPGA-based realization of the FFT processor, suitable for the engineering and technical personnel fpga reference
- 2022-09-26 01:05:03下载
- 积分：1
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sin_wave
在vivado开发环境下，调用ram IP，实现可调频的正弦波信号发生器。(vivado IP signal generator)
- 2020-09-21 23:27:52下载
- 积分：1
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VGA_Controller
用以VGA显示的小程序，很实用，挺有价值的(VGA display for a small program, very practical, quite valuable)
- 2013-07-24 08:58:24下载
- 积分：1
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vhdl按键检测
基于vhdl的按键检测程序。可以有效消除抖动(vhdl key dectect program)
- 2018-02-26 23:48:35下载
- 积分：1
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DLX-pipeline-in-verilog
verilog实现DLX指令集5段流水线(5 stage DLX pipeline implemented in verilog)
- 2013-08-24 22:59:48下载
- 积分：1
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AXI4_Sim
说明： 实现AXI,AXI-Lite乒乓地址的传输，AXI,AXI-Lite已经封装成内核，可直接修改后使用(Realize the transmission of table tennis address of Axi and Axi Lite. Axi and Axi Lite have been encapsulated into a kernel, which can be directly modified and used)
- 2020-05-31 15:20:16下载
- 积分：1
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uart-for-fpga
Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA.
Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit!
The UART controller was simulated and tested in hardware.
- 2020-06-24 22:00:02下载
- 积分：1
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这是改变，你可以找到它在网上视频。
this come from alter ,you can look and find it on line about h263.
- 2022-03-26 07:28:30下载
- 积分：1
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行人交通灯系统设计与7段显示
- 2022-08-09 10:50:36下载
- 积分：1
