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zobrazenie_16_bit_cisla_paralel
16 bit switch input view in hexa format on 7seg display
- 2013-08-16 00:50:49下载
- 积分:1
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air
空调温控电路有限状态自动机,
有TEMP_HIGH和TEMP_LOW
分别与传感器相连用语检测室内温度.-air-conditioning temperature control circuit finite state automaton, and TEMP_LOW TEMP_HIGH with sensors connected to the indoor temperature detection terminology.
- 2022-04-25 13:00:13下载
- 积分:1
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该文件用在CPLD上的,和C语言很接近,5位的计数器一个。
该文件用在CPLD上的,和C语言很接近,5位的计数器一个。-the documents on the CPLD, and the C language is close to that of the five counters one.
- 2023-04-25 23:35:03下载
- 积分:1
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hdmi
HDMI协议的Verilog实现,通过对RGB三个通道分别进行TMDS编码完成,纯原创代码(Verilog implementation of HDMI protocol, through TMDS coding of RGB three channels, pure original code)
- 2020-07-28 16:58:46下载
- 积分:1
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ytupn
Very suitable for the study using computer vision, Analysis of the signal time domain, frequency domain, cepstrum, cyclic spectrum, etc. The performance of the program has reached a high level.
- 2017-09-02 18:07:13下载
- 积分:1
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VHDL分频程序
我用的是二进制分频的方法,这种分频方法的分频只能是2n次方,有限制,但是很方便
- 2022-03-21 03:53:50下载
- 积分:1
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IIC and xlinx official description of spi interface
xlinx官方的iic和spi接口的描述-IIC and xlinx official description of spi interface
- 2022-03-26 12:21:51下载
- 积分:1
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uart
说明: 串口通信通用模块,FPGA Verilog语言 ise,vivado环境(uart,FPGA Verilog, ise,vivado)
- 2020-06-22 07:20:01下载
- 积分:1
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实现了简单的电子表功能,是24小时,用VHDL所编写的,quartus ii 7.2...
实现了简单的电子表功能,是24小时,用VHDL所编写的,quartus ii 7.2-To achieve a simple spreadsheet functions, is 24 hours, using VHDL prepared, quartus ii 7.2
- 2023-05-19 01:30:03下载
- 积分:1
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DLX-pipeline-in-verilog
verilog实现DLX指令集5段流水线(5 stage DLX pipeline implemented in verilog)
- 2013-08-24 22:59:48下载
- 积分:1