登录
首页 » VHDL » 此ip核是xvga视频接口控制器,主要针对xilinx公司的开发工具

此ip核是xvga视频接口控制器,主要针对xilinx公司的开发工具

于 2022-01-25 发布 文件大小:484.67 kB
0 225
下载积分: 2 下载次数: 1

代码说明:

此ip核是xvga视频接口控制器,主要针对xilinx公司的开发工具-This ip is nuclear XVGA video interface controller, the main target Xilinx

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • LED blinker : LED1 blink every second, LED2 blink every minute
    与Xilinx spartan6评估委员会结合的小型项目示例。
    2023-02-03 21:50:03下载
    积分:1
  • count4
    这是一个基于Quartus2 开发环境的4输入加法器( 4adder basic on Quartus2)
    2013-08-04 09:45:07下载
    积分:1
  • verilog编写的32位浮点加法器
    verilog编写的32位浮点加法器-32-bit Floating Point Addition Written in Verilog
    2022-02-21 08:09:50下载
    积分:1
  • 4BITMUIT
    利用LPM_MUIT宏模块设计一个四位数据乘法器(Use LPM_MUIT macro module design a four data Multiplier)
    2013-09-05 10:06:52下载
    积分:1
  • VHDL常用源程序,希望以EDA技术学习者有用!
    VHDL常用源程序,希望以EDA技术学习者有用!-VHDL source code commonly used, I hope to EDA technology learners useful!
    2022-03-22 23:41:46下载
    积分:1
  • Verilog HDL 频率可调的任意波形发生器
    Verilog HDL数字系统设计项目,频率可调的任意波形发生器,可以输出正弦波、方波、三角波和反三角四种波形(Verilog HDL digital system design projects, adjustable frequency arbitrary waveform generator can output sine wave, square wave, triangle wave and the anti-triangular four waveform)
    2011-05-08 03:21:34下载
    积分:1
  • 作者:新舜唐日期:2008
    --author: Suntion Tang --date: 2008-6-7 -- two warning --modify: By Suntion Tang at 2008-6-14 --description: 顶层文件,由于此系统简单, -- 且底层文件不多,故放弃原理图描述,采用VHDL语言描述-author: Suntion Tang date: 2008-6-7 two warning modify: By Suntion Tang at 2008-6-14 description: the top-level documents, as a result of this system is simple, and not more than the bottom of a document, they give up the schematic description of the use of VHDL language description
    2022-04-23 09:59:29下载
    积分:1
  • frequency
    数字频率计,测量范围0-1GHZ,测周测频自动转换,精度极高,花了很长时间,不过还是有一点点小问题,有待改进.(Digital frequency meter, range 0-1GHZ, automatic conversion measured weekly frequency measurement, high precision, took a long time, but still a little small problems to be improved.)
    2011-08-11 00:51:18下载
    积分:1
  • axi_jesd204b
    ADI JESD204接口的ADC与Xilinx FPGA接口IP,包含Verilog和VHDL源代码,AXI总线接口,ADC串行控制接口(ADI IP for interfacing JESD204 ADC to Xilinx FPGA, include Verilog/VHDL source code, AXI interface and serial config interface )
    2021-03-29 15:09:10下载
    积分:1
  • Two_Port_RAM_lab
    Actel双端口存储;通过串口发送数据初始化RAM,然后通过串口返回到上位机的串口调试程序显示(通过串口发送数据初始化RAM,然后通过串口返回到上位机的串口调试程序显示)
    2009-04-03 16:20:30下载
    积分:1
  • 696516资源总数
  • 106571会员总数
  • 2今日下载