登录
首页 » VHDL » 编码器程序

编码器程序

于 2022-01-25 发布 文件大小:105.04 kB
0 159
下载积分: 2 下载次数: 1

代码说明:

用于编码器计数,速度能够达到5ms/1圈,速度很快,而且杂波也很好,能够准确应用。已应用在工程中很多年

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 61EDA_C2212
    红色飓风II开发板USB2FPGA USB驱动程序,由verilog编写,包括源码和FIFO测试程序(Red Hurricane II development board USB2FPGA USB driver from verilog preparation, including source code and test procedures FIFO)
    2013-05-30 14:22:07下载
    积分:1
  • 01_rtc_ds1302
    说明:  实现基于黑金开发板的实时时钟功能,显示时分秒(Realize the real-time clock function based on black gold development board, display time, minute and second)
    2021-01-11 14:40:12下载
    积分:1
  • USB接口控制器参考设计VHDL代码,方便开发FPGA人员进行USB的开发,是一个不错的源码。...
    USB接口控制器参考设计VHDL代码,方便开发FPGA人员进行USB的开发,是一个不错的源码。-USB interface controller reference design VHDL code, facilitate the development of FPGA personnel USB development, is a good source.
    2022-01-23 10:28:51下载
    积分:1
  • fpga_sdram_inst
    nios学习资料,fpga调用外部sdram实例,值得初学者下载。(nios learning materials, fpga call external sdram instance, it is worth beginners to download.)
    2013-08-24 22:26:31下载
    积分:1
  • pgaasm
    is61lv25616简单的verilog程序,完成sram读写 主要是基于FPGA(EP2C8Q208I8)下的SRAM驱动(1lv25616 simple verilog program, complete sram read and w1lv25616 simple verilog program, complete sram read)
    2017-06-19 13:08:08下载
    积分:1
  • 改进的DCT算法设计,veriloghdl实现
    改进的DCT算法设计,veriloghdl实现-Improved DCT algorithm design, veriloghdl realize
    2022-03-07 20:38:18下载
    积分:1
  • ------- ---- WISHBONE Wishbone_BFM IP Core---- -------- ---- This file is par
    ---- ---- ---- WISHBONE Wishbone_BFM IP Core ---- ---- ---- ---- This file is part of the Wishbone_BFM project ---- ---- http://www.opencores.org/cores/Wishbone_BFM/ ---- ---- ---- ---- Description ---- ---- Implementation of Wishbone_BFM IP core according to ---- ---- Wishbone_BFM IP core specification document.--------- ---- WISHBONE Wishbone_BFM IP Core---- -------- ---- This file is part of the Wishbone_BFM project---- ---- http://www.opencores.org/cores/Wishbone_BFM/---- -------- ---- Description---- ---- Implementation of Wishbone_BFM IP core according to---- ---- Wishbone_BFM IP core specification document.
    2022-05-26 15:36:06下载
    积分:1
  • LZRW1 VHDL语言,有有下
    lzrw1算法,VHDL语言,不带TB。模块验证,自己写TB文件
    2023-05-21 19:15:03下载
    积分:1
  • cn60
    六十进制计数器用于计数等操作,代码的实现方式很简单(Six decimal counter for counting operation, the code is very simple implementations)
    2014-12-10 10:10:50下载
    积分:1
  • hdl-master
    ADI ad9361 vivado 下源代码(ADI ad9361 vivado source code)
    2015-08-30 21:39:28下载
    积分:1
  • 696518资源总数
  • 106164会员总数
  • 18今日下载