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基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码，其功能主要有：时间设置，时间显示，跑表，分频，日期设置，日期显示等...
基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码，其功能主要有：时间设置，时间显示，跑表，分频，日期设置，日期显示等-FPGA-based multi-functional Digital Clock Design and Implementation of typhoons and rainstorms are detailed Verilog HDL source code, its functions include: time settings, time display, stopwatch, frequency, date setting, date display
- 2022-02-12 09:36:35下载
- 积分：1
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attachments_2010_01_29
dct and idct vhdl code
- 2010-03-24 23:08:41下载
- 积分：1
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Hexadecimal to 7 segments
Hexadecimal to 7 segments
- 2022-03-07 14:40:55下载
- 积分：1
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AD7608
8通道同步AD芯片7608的FPGA控制程序(FPGA control program of ad7608(8 channel synchronous AD chip))
- 2021-03-13 12:09:24下载
- 积分：1
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HDMI接口编解码传输模块ASIC设计_刘文杰
? 熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。
? 利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。
? 利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。
? 利用双线性插值方法实现对图像640×480到1024×768的放大操作。
? 完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format.
Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface.
With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA.
The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768.
Complete the VGA display interface design.)
- 2020-06-25 04:00:02下载
- 积分：1
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sram_test
is61lv25616简单的verilog程序，完成sram读写(is61lv25616 simple verilog program, complete sram read and write)
- 2013-07-18 11:16:50下载
- 积分：1
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fft64
使用两个8点FFT完成64-point FFT(64-point FFT)
- 2013-01-15 04:57:52下载
- 积分：1
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FPGA verilog代码
说明： 数电实验FPGA verilog代码，包括秒表、全加器、半加器等。(FPGA Verilog code for digital experiment)
- 2020-04-29 11:16:05下载
- 积分：1
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Tutorijal 6
Ovo sto saljem je tutorijal 7 sa vhdlom
- 2018-12-22 06:47:31下载
- 积分：1
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HASH
hash加速器的verilog实现，也用于fpga或asic(hash verilog rtl )
- 2015-01-29 18:48:13下载
- 积分：1
