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一个FPGA
一个基于FPGA的串口程序,已经经过验证,对用FPGA做串口的朋友提供参考和借鉴!-an FPGA-based serial procedures have proven, right Serial do with FPGA reference for a friend and borrow!
- 2022-03-24 10:20:25下载
- 积分：1
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project_1
简单的一个Verilog小程序，适合刚接触的人群(A simple Verilog small program, suitable for people just contact)
- 2020-06-16 22:20:01下载
- 积分：1
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DEMO_CAM_LCD
实现了从摄像头读取数据到液晶的显示，利用了cycloneV 和康欣的开发板资源(It realizes the display of reading data from camera to liquid crystal.)
- 2019-07-05 15:25:36下载
- 积分：1
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an example HDL
an example HDL-Core with any basic gates.
- 2022-12-05 05:05:03下载
- 积分：1
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RC6-block-cipher-using-VHDL
VHDL implementation of RC6 encryption algorithm
Test file represent applying all zero input and all zero key
note that result is correct but bytes positions are swapped
- 2020-12-01 22:09:26下载
- 积分：1
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VGA显示驱动程序编写的Verilog HDL
用Verilog HDL编写的VGA显示驱动程序-Verilog HDL prepared with VGA display driver
- 2022-03-19 09:42:23下载
- 积分：1
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79_ALU
这也是VHDL语言编写的一个小程序，对于VHDL入门很有帮助~~(This is a small program VHDL language, VHDL entry-helpful ~ ~)
- 2013-03-29 11:02:43下载
- 积分：1
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gtx_interface_ip
高速串行设计FPGA-GTX IP设置生成，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接(High-speed serial design FPGA-GTX IP settings generated dynamically configurable rate of 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link)
- 2016-09-22 09:48:00下载
- 积分：1
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uart
通过串口发送，实现FPGA与stm32的dds发生器(Implementation of DDS generator)
- 2018-11-28 09:19:29下载
- 积分：1
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In this case is a convolutional code on a simple algorithm, using verilog HDL la...
本例是关于卷积码的一个简单算法，用verilog HDL语言编写，整个文档包括了产生卷积的整个工程。-In this case is a convolutional code on a simple algorithm, using verilog HDL language, the entire document, including the method of deconvolution of the whole project.
- 2022-02-05 20:03:55下载
- 积分：1
