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DDS
基于ARM的DDS信号发生器设计，可以产生各种信号的波形，生成所需要的信号，可供实验用(DDS signal generator based on ARM, can produce a variety of signal waveform can be used for experiment)
- 2013-03-29 18:49:52下载
- 积分：1
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generic_dpram
IT IS THE DP MEMORY MODULE. IT CONTROLS THE DP MEMORY
- 2013-09-30 19:03:40下载
- 积分：1
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ytupn
Very suitable for the study using computer vision, Analysis of the signal time domain, frequency domain, cepstrum, cyclic spectrum, etc. The performance of the program has reached a high level.
- 2017-09-02 18:07:13下载
- 积分：1
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Verilog串口UART程序
网上关于RS-232的异步收发介绍得很多，最近没事学着摸索用ModelSim来做时序仿真，就结合网上的参考资料和自己的琢磨，做了这个东西。
- 2022-01-26 07:33:30下载
- 积分：1
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JIAOTONGDENG
用VERILOG实现 交通灯控制，且运行正确，希望有帮助(Use VERILOG implementation traffic light control, and operation right, hope to have help)
- 2014-01-05 20:38:03下载
- 积分：1
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gtwizard_254_127_ex_1113_3
配置GTH ip的例子工程，选用7 series 芯片的GTH 113quad的四个通道，在程序中每个链路利用自己的恢复时钟进行数据解码，所以四个通道可以各自独立运行；成功工作在2.54Gb/s的链路状态，长时间（>24小时）的测试，误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)
- 2019-06-17 21:33:56下载
- 积分：1
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视频解码之RGB转YUV模块(Verilog)
资源描述
视频解码之RGB转YUV模块(Verilog)
视频解码之RGB转YUV模块(Verilog)
视频解码之RGB转YUV模块(Verilog)
视频解码之RGB转YUV模块(Verilog)
视频解码之RGB转YUV模块(Verilog)
- 2022-02-25 21:46:18下载
- 积分：1
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RISC-V-Reader-Chinese-v2p1
RISC-V 芯片设计规范,很有参考价值，开源芯片设计必备参考资料，希望对大家有帮助。(The RISC-V Foundation is chartered to standardize and promote the open RISC-V instruction set architecture)
- 2020-07-01 23:00:02下载
- 积分：1
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三八译码器
verilog编写的程序实现三八译码器功能，输入为3位，输出为8位，实现选择的功能。
verilog编写的程序实现三八译码器功能，输入为3位，输出为8位，实现选择的功能
- 2022-02-22 13:23:45下载
- 积分：1
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256点FFT
基2-256点的Verilog HDL代码。具体程序结构说明参考word文档。
- 2022-07-15 07:00:36下载
- 积分：1
