-
LMS
verilog实现的LMS的算法，另外有tb文件可以测试已测试代码正确……(verilog implementation of LMS algorithm, another tb files can test the code has been tested properly ......)
- 2021-03-12 15:29:25下载
- 积分：1
-
ControlUnit
Control Unit VHDL code. Xilinx Spartan 3E board
- 2012-03-15 13:29:40下载
- 积分：1
-
基于EPM1270
基于EPM1270的EProm at24c02 驱动-Based on the EPM1270
- 2022-02-27 00:52:37下载
- 积分：1
-
Uses Verilog the HDL design, obtains the realization basis on
the palm space int...
采用Verilog HDL设计,在掌宇智能开发板上得到实现
根据抢答器的原理，整个电路可划分为三部分：采样电路、门控电路和译码电路- Uses Verilog the HDL design, obtains the realization basis on
the palm space intelligence development board to snatch the answering
principle, the entire electric circuit may divide is three parts: The
sampling electric circuit, the gate control the electric circuit and
the decoding circuit
- 2022-03-16 23:36:15下载
- 积分：1
-
3input_xor
用Hspice实现一个三输入异或门，并分析其功耗和延时。(A three input XOR gate is implemented by Hspice, and its power consumption and delay are analyzed.)
- 2018-06-12 11:06:45下载
- 积分：1
-
JOP of RAM VHDL source code, classic classics, difficult to find a good price.
JOP的RAM VHDL源码，经典的经典，不易找到的好东东，-JOP of RAM VHDL source code, classic classics, difficult to find a good price.
- 2022-10-01 16:00:03下载
- 积分：1
-
一个可以使用的RocketI/O开发实例。基于Xilinx FPGA Virtex5平台。
一个可以使用的RocketI/O开发实例。基于Xilinx FPGA Virtex5平台。-One can use RocketI/O development example. Based on Xilinx FPGA Virtex5 platform.
- 2022-02-12 14:18:54下载
- 积分：1
-
VHDL的循环冗余校验发生器和接收器
VHDL cyclic redundancy check generator und receiver
- 2022-01-23 11:24:26下载
- 积分：1
-
读写FAT32文件系统的SD卡实验
资源描述该程序可以读写FAT32文件系统的SD卡。SD卡的接口现在采用IO模拟接口方式。在板子SD卡座上插上FAT32格式的SD卡，请连接下载线的JTAG接口到板子，下载fpga的SOF文件，再下载NIOSII IDE中的文件。
- 2022-02-09 20:27:01下载
- 积分：1
-
UART_CESHI
基于VHDL语言的串口发送和接收程序,自己调试通过，并已经运用在工程中(Based on the serial port to send and receive procedures VHDL language, its own debugging, and has been used in the project)
- 2016-08-05 15:27:54下载
- 积分：1
