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cpld 控制 8
cpld 控制 8-32M sdram 控制器 maxII epm570实现。
pdf 的说明文件-CPLD control 8-32M sdram controller maxII epm570 realize. pdf documentation
- 2022-01-26 06:46:28下载
- 积分：1
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NIOS II based on the SD CARD MUSIC PLAYER source, including hardware SOPC
基于NIOS II的SD CARD MUSIC PLAYER源码，包括硬件SOPC-NIOS II based on the SD CARD MUSIC PLAYER source, including hardware SOPC
- 2023-02-13 09:35:05下载
- 积分：1
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供大家学习以太网VHDL和Verilog代码
以太网的vhdl和verilog代码，供大家学习-Ethernet VHDL and Verilog code for everyone to learn
- 2022-08-21 10:09:17下载
- 积分：1
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rs232
基于 hdl语言的re232通信实验的设计，程序简单明了，一学就会(rs232 communication)
- 2012-03-26 21:41:47下载
- 积分：1
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clock
数字系统设计报告，多功能电子钟，显示年月日星期时分秒，及校时等功能(Digital system design report, multi-functional electronic bell, show date when the minutes and seconds a week, and school functions when)
- 2009-01-02 16:36:29下载
- 积分：1
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LED
按键控制数码管显示，从0到9显示，八位数码管(Button control digital tube display)
- 2017-11-13 20:19:42下载
- 积分：1
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aiqingmaimai
数字钟蜂鸣器音乐——爱情买卖，很时尚的闹钟音乐代码，经测试，很有感觉。(Digital clock buzzer music- love trading, very stylish alarm clock music code, tested, great feeling.)
- 2020-12-28 01:19:01下载
- 积分：1
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Риторика_Зачетная работа
说明： access must be conf urr arr
- 2019-05-29 20:23:53下载
- 积分：1
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二进制神经网络（BNN）bnn-fpga-master
说明： bnn-fpga是FPGA上CIFAR-10的二进制神经网络（BNN）加速器的开源实现。 加速器针对低功耗嵌入式现场可编程SoC，并在Zedboard上进行了测试。 在编写CIFAR-10测试集中的10000张图像时，错误率是11.19％。(bnn-fpga is an open-source implementation of a binarized neural network (BNN) accelerator for CIFAR-10 on FPGA. The architecture and training of the BNN is proposed by Courbarieaux et al. and open-source Python code is available. Our accelerator targets low-power embedded field-programmable SoCs and was tested on a Zedboard. At time of writing the error rate on the 10000 images in the CIFAR-10 test set is 11.19%.)
- 2020-07-27 07:02:34下载
- 积分：1
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利用vhdl编写的双端口Ram程序，不带数据纠错处理
利用vhdl编写的双端口Ram程序，不带数据纠错处理-VHDL prepared to use dual-port Ram procedures, do not deal with data error correction
- 2023-03-13 05:20:04下载
- 积分：1
