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VHDL程序
利用QuartusⅡ6.0对所设计的出租车计费器的VHDL代码进行仿真，并在FPGA数字实验系统上实现了该控制。(The Quartus II 6 is used to simulate the VHDL code of the designed taxi billing device, and the control is realized on the FPGA digital experiment system.)
- 2017-12-14 12:35:23下载
- 积分：1
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H.264编解码的VHDL语言写的
这里描述的VHDL源代码由若干模块下的释放
- 2022-04-18 20:33:11下载
- 积分：1
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my_uart
一个简单的UART串口程序，能实现数据的发送与接收，但没有奇偶校验等验证数据传输是否正确。(A simple UART serial program, can send and receive data, but there is no parity and other validation data is correct.)
- 2011-08-17 20:48:11下载
- 积分：1
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等精度测频率
说明： 利用stm32F407实现的等精度测频，可以精确测量频率，误差很小(The equal precision frequency measurement realized by stm32F407 can accurately measure frequency with little error.)
- 2020-06-19 13:00:02下载
- 积分：1
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VHDL写的串口，很好用，程序非常简单，可以调试用
VHDL写的串口，很好用，程序非常简单，可以调试用-Written in VHDL serial, very good, and the procedure is very simple, you can debug with
- 2022-08-08 18:58:10下载
- 积分：1
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QPSK
说明： 基于FPGA的QPSK调制解调电路设计与实现 (QPSK)
- 2010-04-07 14:15:21下载
- 积分：1
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Nios-II
数字电路的设计。以软件方式实现硬件电路，功能强大，开发容易。(Digital circuit design. With software to realize the hardware circuit, powerful, development easy.
)
- 2011-12-03 09:47:56下载
- 积分：1
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这里面有许多vhdl的例子，相信对这语言的初学者受益匪浅
这里面有许多vhdl的例子，相信对这语言的初学者受益匪浅-There are many examples of vhdl, I believe that beginners benefit from this language
- 2023-06-28 10:40:04下载
- 积分：1
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FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输，已验证，直接可用...
FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输，已验证，直接可用-FPGA VERILOG using DCFIFO realize cross-clock domain data transfer, has been verified, directly available
- 2022-04-17 14:15:55下载
- 积分：1
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i2c
说明： 本文研究的IIC总线控制器具有如下特征
1.兼容飞利浦I2C标准，以主机模式与外围设备进行数据通信，对IIC从机模型进行读/读，读/写，写/写，写/读[18]。
2.多主操作
3.软件可编程时钟频率
4.时钟拉伸和等待状态生成
5.软件可编程确认位
6.时钟同步设计
7.仲裁中断丢失，自动转移取消
8.开始/停止/重复启动检测/确认生成
9.总线忙检测(The IIC bus controller studied in this paper has the following characteristics.
1. Compatible with Philips I2C standard, data communication between host mode and peripheral devices, read/read, read/write, write/write, write/read for IIC slave model [18].
2. Multiple Main Operations
3. Software programmable clock frequency
4. Clock stretching and waiting state generation
5. Software Programmable Confirmation Bit
6. Clock Synchronization Design
7. Loss of arbitration interruption and cancellation of automatic transfer
8. Start/Stop/Repeat Start Detection/Verification Generation
9. Bus busy detection)
- 2019-06-18 12:18:10下载
- 积分：1
