在这个项目中我们使用 DE2 115 板上显示每次通过转移在左边按下某个键滚动你好。 这种架构使用管道和多路复用器

ep2c5 实现 逻辑门 verilog语言，quartus 2 仿真-ep2c5 the realization of logic gates verilog language, quartus 2 Simulation

vhdl编写的fifo程序-VHDL procedures prepared by the fifo

两位独立数码管100进制计数器，每1秒计数一次。从0到99，到99后又回到0.-Two independent 100-band digital tube counters, every time 1 seconds count. From 0 to 99, to 99 and then back to 0.

PCIe demo sample code

详细的说明了FPGA设计的整个流程 FPGA设计全流程Modelsim>>Synplify.Pro>>ISE(Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE)

当年本科时的毕业设计，信号发生器和频率计-The time of the year undergraduate graduate design, signal generator and frequency counter

本例介绍直接合成带阻滤波器的方法，n阶滤波器能实现n个传输零点(A direct synthesis technique of a new class of bandstop coupled resonator elliptic filters is presented. Two different coupling schemes, which both include source–load coupling are used. The first coupling and routing scheme is the standard folded structure used in implementing bandpass elliptic filters with transmission zeros using resonators.)

说明：  简单的一个Verilog小程序，适合刚接触的人群(A simple Verilog small program, suitable for people just contact)

用VHDL语言设计多功能的电子表。实现基本电子表的时间显示、闹钟、秒表等功能(VHDL language design with multi-functional electronic watch. The time table to achieve basic electronic display, alarm clock, stopwatch functions)