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CNT4
说明： 4位二进制加法计数器的两种不同VHDL的描述,与比较。(4-bit binary addition of two different counter VHDL description, and more.)
- 2010-04-13 22:20:44下载
- 积分：1
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数控分频的一个工程
数控分频的一个工程---包括vhdl源程序和编译后产生的相关文件-CNC dividing frequency of a project- including VHDL source code and compile the relevant documents after
- 2022-05-22 23:30:57下载
- 积分：1
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29_ad9226_test
用Verilog编写ad_9866的相应程序，在FPGA上实现相应功能(The corresponding program of ad_9866 is written with Verilog, and the corresponding functions are realized on the FPGA.)
- 2019-06-24 16:43:27下载
- 积分：1
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submodule
verilog 双模块算术平均值计算模块，子模块在时钟上升沿技术，高层模块根据当前计数值计算算数平均(verilog double module arithmetic mean calculation module, sub-module in the clock rising edge technology, high-level module is calculated based on arithmetic average of the current count)
- 2011-01-05 22:49:16下载
- 积分：1
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数字频率计 FPGA 用verilog语言编写
数字频率计 FPGA 用verilog语言编写-Digital Cymometer verilog language used FPGA
- 2023-01-25 21:10:03下载
- 积分：1
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buffer
用verilog实现的buffer，经过了fpga平台验证。(Implement buffer with verilog.)
- 2020-10-28 12:19:58下载
- 积分：1
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It is then register ( shifter) PISO ( Parallel
It is then register ( shifter) PISO ( Parallel - in, serial - out)-It is then register ( shifter) PISO ( Parallel- in, serial- out)
- 2022-03-14 08:29:42下载
- 积分：1
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DW_apb_wdt
verilog实现watch dog，可直接用于芯片开发中。(erilog realization watchdog, can be directly used for chip development.)
- 2020-12-25 16:09:06下载
- 积分：1
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用硬件描述语言编程实现减法器,实现两个操作数的减法
用硬件描述语言编程实现减法器,实现两个操作数的减法-Using hardware description language programming subtraction, and the achievement of the two operands of the subtraction
- 2022-06-29 17:16:40下载
- 积分：1
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GIF图像查看器的VHDL代码
vhdl code for GIF Image Viewer
- 2023-05-09 12:40:03下载
- 积分：1
