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VHDL由IEEE 1076标准定义的，IEEE标准的VHDL语言参考人…
VHDL is defined by IEEE Standard 1076, IEEE Standard VHDL Language Reference Manual (the VHDL LRM). The original standard was approved in 1987. IEEE procedures require that standards be periodically reviewed and either reaffirmed or revised. The VHDL standard was revised in 1993, 2000, and 2002. In each revision, new language features were added and some existing features enhanced. The aim in each revision was to improve the language as a tool for design and verification of digital systems.
Since the 2002 revision, there have two parallel efforts to further develop the language. The first was the VHDL Procedural Interface (VHPI) Task Force, a subcommittee of the IEEE P1076 Working Group. The VHPI Task Force prepared an interim amendment to the standard, formally approved by IEEE in March 2007. The amendment is titled IEEE 1076c, Standard VHDL Language Reference Manual―Amendment 1: Procedural Language Application Interface.
- 2023-05-31 06:40:03下载
- 积分：1
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encoding-decoding
卷积码编码译码程序以及其modelsim仿真波形文件等(Convolutional code encoding and decoding procedures and the Modelsim simulation waveform file)
- 2020-12-27 20:59:03下载
- 积分：1
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HDB3modelsim
HDB3编码通过verilog实现，通过modelsim仿真(HDB3 coding is implemented by Verilog and simulated by Modelsim)
- 2020-06-18 05:20:02下载
- 积分：1
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add4bit
一位全加器的VHDL源码与TEST BENCH.XILINX下通过(A full adder and the VHDL source code through TEST BENCH.XILINX)
- 2009-07-20 08:18:37下载
- 积分：1
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Hardware-CNN-master
Convolutional neural network code for fpga
- 2019-02-27 15:21:22下载
- 积分：1
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使用vriloge硬件描述语言设计数字频率计，其对于高频测量精确，可测范围0―99999999HZ，在MAX+PLUSII中运行通过并在实验箱上运行通过达到要求...
使用vriloge硬件描述语言设计数字频率计，其对于高频测量精确，可测范围0―99999999HZ，在MAX+PLUSII中运行通过并在实验箱上运行通过达到要求-The use of hardware description language design vriloge digital frequency meter, and its high-frequency measurement for accurate, range 0-99999999HZ, in MAX+ PLUSII run me through and run the experiment to meet the requirement through
- 2022-01-25 18:01:01下载
- 积分：1
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polar_SC译码
该部分的主要功能是完成基于FPGA的polar码SC译码。(The main function of this part is to complete the FPGA-based polar code SC decoding.)
- 2021-02-17 13:49:46下载
- 积分：1
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usbd_ucos
基于ALINX AX7020硬件平台的USB-OTG通信程序。操作系统采用uCOS III v1.41，基本实现了双向USB2.0 块传输（Bulk Transfer）通信，zynq的PS端接收USB数据并回传至主机。经测试，主机端Window10系统采用libUSBK编程时，采用64字节的块时，传输速率可达210Mbps。zynq开发工具为Vivado2015.4，程序包中包含了全部的硬件和软件工程文档。(A USB-OTG communication project where an AX7020 platform is employed as USB device. The embeded operating system is uCOS III of version 1.41, and the FPGA toolchain is Vivado 2015.4. This project implements a full speed bidirectional USB2.0 bulk transfer. A test on Windows 10 host with libUSBK shows that the transfer speed is up to 201Mbps.)
- 2020-09-09 09:38:02下载
- 积分：1
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12
说明： 用FPGA进行等精度频率和相位差测量的程序，本程序是在EPEC6Q240C8下的程序(Carried out with the FPGA such as the frequency and phase measurement precision of the procedure, this procedure was the procedure under the EPEC6Q240C8)
- 2010-03-03 17:42:11下载
- 积分：1
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Pipeline-2
Pipeline processor verilog components
- 2012-12-21 17:53:18下载
- 积分：1
