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WigglerJTAG
Wiggler Clone .JTAG Schematic and PCB in Altium Designer Format
- 2009-07-17 19:27:27下载
- 积分：1
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"；Verilog HDL设计指南"；5
《Verilog HDL 程序设计教程》5-"Verilog HDL Design Guide" 5
- 2022-04-21 22:39:14下载
- 积分：1
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using VHDL prepared by the LED display driver circuit design source
用VHDL语言编写的LED显示器驱动电路的设计源程序-using VHDL prepared by the LED display driver circuit design source
- 2023-07-22 14:55:03下载
- 积分：1
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RS码译码器
采用VHDL语言实现基于ＢＭ算法的ＲＳ译码器，附件为整个工程文件，内附波形仿真图。程序在QUARTUS II 9.0下仿真通过
- 2022-06-03 16:19:45下载
- 积分：1
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全加器的VHDL程序实现及仿真
全加器的VHDL程序实现及仿真-full adder VHDL simulation program and
- 2022-02-03 16:51:49下载
- 积分：1
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集成电路的I2C协议间
inter integrated circuit i2c protocol
- 2022-02-03 10:59:46下载
- 积分：1
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FPGA-implementation
重点介绍了双线性插值算法和该方法的Ｆ Ｐ ＧＡ硬件实现
方法， 包括图像数据缓冲单元、 插值系数生成单元以及插值计算单元等。(Highlights the bilinear interpolation algorithm and the method of F P GA hardware
The method includes an image data buffer unit, the interpolation coefficient generating unit and an interpolation computing unit and the like.)
- 2021-05-14 18:30:02下载
- 积分：1
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《CPLDFPGA verilog DA0832调控
verilog da0832 cpldfpga control-verilog da0832 cpldfpga control
- 2022-12-07 05:55:03下载
- 积分：1
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Study the performance of state machine. Rar inspect the performance of state mac...
状态机的性能考察.rar
状态机的性能考察.rar-Study the performance of state machine. Rar inspect the performance of state machine. Rar
- 2023-04-13 19:15:04下载
- 积分：1
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本设计是针对LEON3 Altera Nios II startix2
This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the
- 2022-05-18 19:00:04下载
- 积分：1
