-
Kluwer.Academic.The.Verilog.Hardware.Description
Kluwer academic the verilog hardware description language fith edition
- 2014-10-08 08:11:42下载
- 积分：1
-
HUAWEI_FPGA
华为内部资料，华为FPGA全套资料，包括华为的专利设计(Internal information Huawei Huawei FPGA complete information, including Huawei' s patented design)
- 2020-12-21 18:19:08下载
- 积分：1
-
EnDat
ENDAT 协议说明，包括时序等详细的说明，(endat Encoder characteristics)
- 2021-05-12 22:30:02下载
- 积分：1
-
ALTERA嵌入式设计大赛获奖作品文章，非常适合DE2开发参考
ALTERA嵌入式设计大赛获奖作品文章，非常适合DE2开发参考-ALTERA Embedded Design Competition Prize-winning article, very suitable for the development of reference DE2
- 2022-04-07 11:00:16下载
- 积分：1
-
一个模拟ISA界面的简易小程式，简单易懂
一个模拟ISA界面的简易小程式，简单易懂-ISA interface, a simple simulation of a small program, easy-to-read
- 2022-07-24 01:55:08下载
- 积分：1
-
RapidIO_avalonst
RapidIO：使用Avalon-ST直通接口的实现方法，可以在fpga上实现(rapidio altera)
- 2017-05-31 22:50:11下载
- 积分：1
-
word_aligner_8bit_test
CMV2000的对齐模块，适用于其他对齐模块，自行修改(CMV2000 alignment module, suitable for other alignment modules, self-modifying)
- 2020-06-16 07:00:01下载
- 积分：1
-
Low
低通滤波器在QUARTUS7.0开发环境下的文本与框图结合的实现方法的源代码-Low-pass filter QUARTUS7.0 development environment in the text and diagram combination of methods to achieve source code
- 2022-11-29 01:15:03下载
- 积分：1
-
VHDL实现SPI功能源代码
VHDL实现SPI功能源代码
-- The SPI bus is a 3 wire bus that in effect links a serial shift
-- register between the "master" and the "slave". Typically both the
-- master and slave have an 8 bit shift register so the combined
-- register is 16 bits. When an SPI transfer takes place, the master and
-- slave shift their shift registers 8 bits and thus exchange their 8
-- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
- 2022-01-26 00:50:40下载
- 积分：1
-
VHDL language learning paradigm, the FSK
学习VHDL语言的范例，有关FSK-VHDL language learning paradigm, the FSK
- 2023-06-01 13:25:03下载
- 积分：1
