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FPGA_Timing_Constraints_byCamp
简要地说明时序约束的内容，对入门级的朋友相当起到引导的作用(Briefly describes the content of timing constraints on entry-level friends rather play a guiding role)
- 2013-10-30 23:20:53下载
- 积分：1
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verilogdct
dct实现verilog hdl的数字图像处理，源代码(dct achieve verilog hdl digital image processing, source code)
- 2020-12-02 17:49:26下载
- 积分：1
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ozgul2013
Digital pre-distortion (DPD) is an advanced digital
signal-processing technique that mitigates the effects of power
amplifier (PA) nonlinearity in wireless transmitters. DPD plays
a key role in providing efficient radio digital front-end (DFE)
solutions for 3G/4G basestations and beyond. Modern FPGAs
are a promising target platform for the implementation of flexible
wireless DFE solutions, including DPD.
- 2019-01-05 18:20:30下载
- 积分：1
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rc6_decryption
rc6 algorithm designed based on verilog and is verified
- 2020-12-01 21:59:28下载
- 积分：1
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本代码是实现了lwip协议栈,可以移植到其他类型的嵌如式操作系统上
本代码是实现了lwip协议栈,可以移植到其他类型的嵌如式操作系统上-This code is to achieve a lwIP protocol stack can be ported to other types of embedded operating systems such as the type
- 2022-03-18 10:40:22下载
- 积分：1
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moore 状态机的一个简单的事例，初学者很好的地实例！
moore 状态机的一个简单的事例，初学者很好的地实例！-moore state machine of a simple example for beginners to very good example!
- 2022-08-03 06:34:52下载
- 积分：1
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Decimal precision counts, classic written, easy learning and reference for all t...
十进制精确计数，经典写法，便于学习与参考，供大家分享-Decimal precision counts, classic written, easy learning and reference for all to share
- 2022-03-24 02:37:10下载
- 积分：1
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VHDL-SUBWAY
基于QuartusII环境下的地铁自动售票系统(Subway auto ticketing system based on QuartusII)
- 2011-04-20 09:35:24下载
- 积分：1
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fir_512_378_mux
512阶高速FIR成型滤波器，四相位复用，树形加法和多级流水线结构。(512-order high-speed FIR shaping filter, four-phase re-use, tree addition and multi-stage pipeline structure.)
- 2009-10-14 18:25:24下载
- 积分：1
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PL_2FSK
基于VHDl的2FSK调制！用的是altera的quartus11软件(Based on VHDl the 2FSK modulation)
- 2012-12-13 17:20:54下载
- 积分：1
