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ALTERA NIOS处理器实验，编程环境是QUARTUS，在NIOS SHELL下编译实现功能。实验USB接口...
ALTERA NIOS处理器实验，编程环境是QUARTUS，在NIOS SHELL下编译实现功能。实验USB接口-Altera NIOS processor experiments, programming environment is QUARTUS in NIOS SHELL compiler functionality. Experimental USB interface
- 2022-05-25 15:09:52下载
- 积分：1
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SCAN_LED
基于EDA技术中的对LED扫描电路的实验，程序能成功运行，能直接在开发板上看实验结果(EDA-based LED technology to scan the experimental circuit, the program can run successfully, can see directly in the development of on-board results)
- 2009-06-05 11:49:53下载
- 积分：1
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pipline_lms_and_rls_verilog
流水线LMS，和RLS算法的Verilog代码，用于自适应信号处理的FPGA实现。(The Verilog code about fir_pipline_lms and fir_rls. They commonly used in adaptive signal processing in FPGA platform.)
- 2021-05-06 20:58:37下载
- 积分：1
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D_flip
source vhdl code of D flipflop logic
- 2011-03-18 17:49:28下载
- 积分：1
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一个latch3 VHDL编写。
A latch3 written in VHDL.
- 2022-04-15 06:24:21下载
- 积分：1
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QPSK
用Verilog语言实现QPSK调制，QPSK是一种数字调制方式。它分为绝对相移和相对相移两种。
(Verilog language using QPSK modulation, QPSK is a digital modulation. It is divided into absolute and relative phase shift of the phase shift of two.)
- 2011-01-24 17:46:44下载
- 积分：1
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Xilinx CPLD源代码，使用XC9500系列CPLD,驱动液晶
Xilinx CPLD源代码，使用XC9500系列CPLD,驱动液晶-Xilinx CPLD source code, use the XC9500 series CPLD, LCD Driver
- 2023-03-07 15:05:03下载
- 积分：1
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bjgm
四间隔频率变化，并循环输出50~51ms之间的频率。(Four-interval frequency changes and the cycle between 50 ~ 51ms output frequency.)
- 2008-08-21 11:46:20下载
- 积分：1
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Verilog的150个经典设计实例
Verilog经典实例.包括洗衣机红路灯、兹自动方麦基、等式子可用(Classic examples of Verilog. Including red street lights for washing machines, ZAM, equation availability)
- 2021-03-17 16:49:20下载
- 积分：1
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total
一个简单的后台模板，主要为贵金属直播室有喊单等功能类型的。
ps：由于涉及到iframe本地跨域问题，因此查看时请在服务器上进行审阅。(A simple background template, mainly for the precious metal living room, such as the type of function.
PS: as a result of the local cross domain problem involved in the iframe, so check it out on the server.)
- 2015-11-18 09:00:49下载
- 积分：1
