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UDP
用verilog实现的UDP协议，包括arp，udp，ip分段协议等，对于想用FPGA实现TCP/IP协议的人来说，应该会起到一定的帮助作用(Implemented with verilog UDP protocols, including arp, udp, ip fragmentation protocol, etc., who want to achieve TCP/IP protocol with the FPGA people, should play a helpful role)
- 2021-04-05 04:39:03下载
- 积分：1
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8位数字显示的简易频率计
（1）能够测试10HZ~10MHZ的方波信号；
（2）电路输入的基准时钟为1HZ，要求测量值以8421BCD码形式输出；
（3）系统有复位键；
（4）采用分层次分模块的方法，用Verilog HDL进行设计，并对各个模块写出测试代码；
（5）具体参照说明文档（包含源代码，仿真图，测试波形，详细的设计说明）(A square wave signal capable of testing 10HZ~10MHZ;
(2) the reference clock input by the circuit is 1HZ, and the measured value is output in the form of 8421BCD code;
(3) the system has a reset key;
(4) adopt the method of layering sub sub module and design with Verilog HDL;
(5) write test simulation program.)
- 2020-12-02 02:59:26下载
- 积分：1
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海力士公司8M字节的SDR SDRAM实现Verilog仿真语言。
Hynix公司8M byte sdr sdram的verilog语言仿真实现。-Hynix company 8M byte sdr sdram realize the Verilog simulation language.
- 2023-07-14 06:05:04下载
- 积分：1
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galois
example of BCH and RS codecs
- 2009-06-10 11:26:17下载
- 积分：1
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通信协议AHB_LITE
AHB_Lite 通信协议的FPGA Verilog 设计(AHB_Lite communication protocol Verilog design in FPGA)
- 2020-12-15 10:09:14下载
- 积分：1
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Using VHDL language driver DM128* 64LCD procedures
用VHDL 语言驱动DM128*64LCD程序-Using VHDL language driver DM128* 64LCD procedures
- 2022-07-09 01:28:22下载
- 积分：1
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基于sopc的IIC总线设计完整设计sopcIIC
该例子是基于sopc的IIC总线设计完整设计，分为硬件和软件部分，软件部分是用c语言编写的。该项目是个以完成的项目，据有较高的参考和经济价值。该例子是原来做过的项目。 整个项目是在Quartus II 7.0和nios IDE环境下开发。
(This example is based on the IIC bus design sopc complete design, divided into hardware and software, the software part is written in c language. The project is to complete the project, according to the reference and a higher economic value. The example is a project originally done. The whole project is in the Quartus II 7.0 and the nios IDE development environment.)
- 2020-07-12 00:58:53下载
- 积分：1
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blocking
基于verilog语言的数据选择器，包括数据选择器的测试模块
(verilog language based on the data selector, including data selection for the test module)
- 2007-03-22 09:05:10下载
- 积分：1
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ambe_rx_tx
AMBE2000的压缩数据输出输入的Verilog代码，实现了自回环（loopback）效果. 希望对学习verilog语言的同学有所帮助。(The Verilog code of AMBE2000. input and output of compressed data to achieve a self-loop (loopback) effect. hope to help the one who is studying the verilog language.)
- 2014-03-19 08:55:46下载
- 积分：1
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FPGA控制AG9226代码
FPGA控制AG9226进行采样的代码,并用signaltap测试了一下其正确性
- 2022-07-21 15:41:56下载
- 积分：1
