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verilog_median_filter
图像处理的中值滤波器，使用verilog开发环境编程实现。(Verilog development environment programming median filter)
- 2016-01-24 16:54:32下载
- 积分：1
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rc6_decryption
rc6 algorithm designed based on verilog and is verified
- 2020-12-01 21:59:28下载
- 积分：1
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The design of digital self
数字平律己的设计非常实用 黄永显示早设计大方ijasd-The design of digital self-Ping Wong Wing-show as early as practical design Dafang ijasd
- 2022-08-10 00:17:42下载
- 积分：1
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doorlock
基于FPGA设计的电子密码锁是一个小型的数字系统，与普通机械锁相比，具有许多独特的优点：保密性好，防盗性强，可以不用钥匙，记住密码即可开锁等。(FPGA-based design of the electronic code lock is a small digital system. It has many unique advantages：good privacy and security , it do not need the key but remember password to unlock, and so on while it compare to ordinary mechanical locks.)
- 2013-12-25 21:24:41下载
- 积分：1
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本实施multilplier在vhdl.this源代码是有用的电脑学习…
this implemented multilplier in vhdl.this source code is useful for computer student and hardware engineering.-this is implemented multilplier in vhdl.this source code is useful for computer student and hardware engineering.
- 2022-01-31 00:27:28下载
- 积分：1
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FIR_poroje
this project is about FIR FIlter By VHdl codes in the ISE.
- 2013-09-29 19:25:16下载
- 积分：1
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用VHDL语言编写的实现8位数据的并串转换，可下载在FPGA中
用VHDL语言编写的实现8位数据的并串转换，可下载在FPGA中-VHDL language with the realization of an 8-bit data, and the string conversion, can be downloaded in the FPGA in
- 2022-04-15 10:43:06下载
- 积分：1
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BNN-PYNQ-master
在PYNQ-Z1上搭建二值神经网络(BNN)(Building two value neural network (BNN) on PYNQ-Z1)
- 2018-01-15 11:34:33下载
- 积分：1
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cpu_easy
ADD MOV MOVi SUB四指令cpu设计，qutartus，(Design of four-instruction CPU)
- 2019-05-13 11:44:49下载
- 积分：1
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pinlvji
使用FPGA测量频率大小，并且在数码管上进行显示(Frequency measurement using FPGA and display on digital tube)
- 2020-06-18 10:20:02下载
- 积分：1
