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FPGA简:讲述了FPGA的基本概念、结构、发展
FPGA简:讲述了FPGA的基本概念、结构、发展-Jane FPGA: FPGA describes the basic concepts, structure, development
- 2022-03-10 18:57:06下载
- 积分：1
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基于FPGA的高性能32位浮点FFTIP核的开发，适合fpga工程技术人员参考...
基于FPGA的高性能32位浮点FFTIP核的开发，适合fpga工程技术人员参考-FPGA-based high-performance 32-bit floating-point nuclear FFTIP development, engineering and technical personnel for reference fpga
- 2022-10-24 15:10:04下载
- 积分：1
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exercise3
用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)
- 2013-08-30 11:12:09下载
- 积分：1
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bit
// Data port, granularity 8
// -*- Mode: Verilog -*-
// Filename : wb_master.v
// Description : Wishbone Master Behavorial
// Author : Winefred Washington
// Created On : 2002 12 24
// Last Modified By: .
// Last Modified On: .
// Update Count : 0
// Status : Unknown, Use with caution!
// Description Specification
// General Description: 8, 16, 32-bit WISHBONE Master
// Supported cycles: MASTER, READ/WRITE
// MASTER, BLOCK READ/WRITE
// MASTER, RMW
// Data port, size: 8, 16, 32-bit
// Data port, granularity 8-bit
// Data port, Max. operand size 32-bit
// Data transfer ordering: little endian
// Data transfer sequencing: undefined-//-*- Mode: Verilog-*-
// Filename : wb_master.v
// Description : Wishbone Master Behavorial
// Author : Winefred Washington
// Created On : 2002 12 24
// Last Modified By: .
// Last Modified On: .
// Update Count : 0
// Status : Unknown, Use with caution!
// Description Specification
// General Description: 8, 16, 32-bit WISH
- 2023-03-16 01:05:04下载
- 积分：1
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12
说明： 用FPGA进行等精度频率和相位差测量的程序，本程序是在EPEC6Q240C8下的程序(Carried out with the FPGA such as the frequency and phase measurement precision of the procedure, this procedure was the procedure under the EPEC6Q240C8)
- 2010-03-03 17:42:11下载
- 积分：1
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VHDL代码登记并决定如何登记
vhdl code for register and detemines how register
works -vhdl code for register and detemines how register
works
- 2022-06-18 22:43:42下载
- 积分：1
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sparc org, vhdl rtl code
sparc org, vhdl rtl code
- 2022-04-19 15:34:55下载
- 积分：1
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vhdl
说明： vhdl常见小实验代码，包括二进制比较器，4选1,8421十进制，8421转化成格雷码，8421余三码，分频器，数据码译码器，二进制减计数器，四位环形计数器等(VHDL common small experiment code)
- 2020-06-24 13:00:02下载
- 积分：1
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Using VHDL hardware language to achieve the top level of the IIC control procedu...
用VHDL硬件语言实现的iic顶层控制程序-Using VHDL hardware language to achieve the top level of the IIC control procedures
- 2022-12-20 20:00:08下载
- 积分：1
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verilog实现基于i2s协议接口 i2s_interface
verilog实现基于i2s协议接口，在fpga上验证通过。(Verilog implements the interface based on I2S protocol and verifies it on fpga.)
- 2017-11-05 17:26:39下载
- 积分：1
