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Block-cipher-lock
密码锁verilog源代码，包括四个七段数码管显示模块，设置密码以及输入密码校验模块(Password lock Verilog source code, including four of seven digital tube display module, set the password and password verification module)
- 2014-01-11 23:57:19下载
- 积分：1
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6级流水，verilog实现浮点数的加法，其中浮点数格式符合IEEE754标准...
6级流水，verilog实现浮点数的加法，其中浮点数格式符合IEEE754标准-6 water, verilog realize the floating point adder, in which floating-point format in line with the IEEE754 standard
- 2023-09-01 12:35:04下载
- 积分：1
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qpsk
QFSK的调制与解调，用C写的主程序，汇编写的调制与解调的子程序(QFSK the modulation and demodulation, with the main program in C, compile writing, the modulation and demodulation of the Subprogram)
- 2020-07-01 19:20:02下载
- 积分：1
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100例VHDL语言解释，北京理工大学毕业…
VHDL语言100例详解，北京理工大学ASIC研究生出版，这里是51~94个examples-VHDL language of 100 cases explain, Beijing Institute of Technology, Graduate ASIC publication, here is the 51 ~ 94 examples
- 2022-04-16 00:12:16下载
- 积分：1
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breathingLED
stc12c5a60s2单片机做的两路呼吸灯，可以用ad和按键控制闪动频率(stc12c5a60s2 SCM done with the two breathing lights, you can use the ad and buttons to control the flashing frequency)
- 2013-05-10 15:33:18下载
- 积分：1
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zuixiangxide_NIOS_kaifajiaocheng
来自于NIOSII的那些事，该书详细地介绍了NIOSS的使用过程，非常适合初学者。(From the NIOSII those things, the book are detailed in this paper NIOSS use process, very suitable for beginners.
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- 2011-12-13 11:33:57下载
- 积分：1
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adaptive
这是基于MATLAB编程实现自适应滤波器，并在XILINX的FPGA上硬件可实现的模型文件(This is based on the MATLAB programming adaptive filter, and the XILINX' s FPGA hardware can be a model document)
- 2009-06-24 13:26:32下载
- 积分：1
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abi123
encoding and decoding of audio signal
- 2013-02-02 18:59:16下载
- 积分：1
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uart_tr(3)
uart_tr 异步串口通信主机 使用verilog HDL语言编写(uart_tr the host of the uart )
- 2015-06-08 21:02:17下载
- 积分：1
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Can realize the time digital clock display, and on the hours, minutes, seconds t...
能实现数字钟中时间的显示，并可对小时，分钟，秒进行调整-Can realize the time digital clock display, and on the hours, minutes, seconds to adjust
- 2022-04-29 18:33:18下载
- 积分：1
