-
组合电路的设计8位加法器设计(ADD8.vhd)
组合电路的设计8位加法器设计(ADD8.vhd)-Combinational Circuit Design 8-bit adder design (ADD8.vhd)
- 2022-10-25 12:35:04下载
- 积分：1
-
xapp1248
说明： Implementing SMPTE SDI Interfaces with UltraScale GTH Transceivers
- 2019-12-06 17:24:49下载
- 积分：1
-
通过VHDL语言的例子，FPGA的VHDL语言的原型（八）是
应用背景FPGA原型的VHDL例子提供一系列清晰，易于遵循的快速代码开发模板；大量的实际例子来说明和强化的概念和设计技术；现实可实施的项目和测试在Xilinx原型板；深入探索和Xilinx PicoBlaze软核微处理器。关键技术本书采用“做中学”介绍VHDL和FPGA技术的概念和设计人员通过一系列的实验方法。
- 2022-03-18 12:23:37下载
- 积分：1
-
Program to implement convolution through VHDL
Program to implement convolution through VHDL-Program to implement convolution through VHDL...
- 2023-02-08 06:15:02下载
- 积分：1
-
base_4_fft
基4FFT原理及MATLAB实现，基本原理，编程思想等(base——4 FFT principle and MATLAB implementation, the basic principles of programming ideas, etc.)
- 2016-01-28 16:52:37下载
- 积分：1
-
fpga
pid算法控制电机运动，实现fpga与dsp的双口RAM通信(PID algorithm to control motor movement, the realization of FPGA and DSP dual port RAM communication)
- 2020-12-08 20:39:20下载
- 积分：1
-
Quartusrs232
串口通讯，与硬件联通调试过，收发程序是分开的。(Serial Communication)
- 2009-05-04 14:53:06下载
- 积分：1
-
Typical examples of character LCD interface 10.8 The Design and Implementation o...
典型实例10.8 字符LCD接口的设计与实现
软件开发环境：ISE 7.1i
硬件开发环境：红色飓风II代－Xilinx版
1. 本实例控制开发板上面的LCD的显示；
2. 工程在project文件夹里面
3. 源文件和管脚分配在
tl文件夹里面
4. 下载文件在download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Typical examples of character LCD interface 10.8 The Design and Implementation of Software Development Environment: ISE 7.1i development environment hardware: Hurricane II on behalf of the red-Xilinx Edition 1. The above examples of the control board of the LCD display 2. Projects project folder inside 3. the distribution of the source file and pin in rtl folder inside 4. download files in download folder inside,. mcs file for the PROM mode download,. bit for the JTAG debugger to download the file.
- 2022-07-15 02:45:21下载
- 积分：1
-
counter
设计一个十进制计数器模块，输入端口包括 reset、up_enable 和 clk，输出端口为 count
和 bcd，当 reset 有效时（低电平），bcd 和 count 输出清零，当 up_enable 有效时（高电
平），计数模块开始计数（clk 脉冲数），bcd 为计数输出，当计数为 9 时，count 输出一
个脉冲（一个 clk周期的高电平，时间上与“bcd=9”时对齐）(Design of a decimal counter module, input port, including the reset up_enable clk, output port for the count and bcd, when reset is active (low), the bcd and count output cleared up_enable active (high), count module starts counting the (the CLK pulse number), the BCD count output when the count 9, the count output of the high level, the time of a pulse (a clk cycle with " bcd = 9" when aligned))
- 2013-04-13 19:53:29下载
- 积分：1
-
youmui_v20
ICA (Principal Component Analysis) algorithm and procedures, GSM is GMSK modulation signal generation, On neural network control.
- 2017-09-01 20:51:26下载
- 积分：1
