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xilinx CTC IPcore(encoder 和 decoder）的标准测试，未经信道加噪
xilinx CTC IPcore(encoder 和 decoder）的标准测试，未经信道加噪-the standard test of xilinx CTC IPcore (encoder and decoder) , without the channel with noise
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- 积分：1
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gold
基于vhdl语言的15位gold序列的设计的开端一部分程序(Vhdl language based on sequences of the 15 gold as part of the beginning of the design process)
- 2011-05-16 21:48:38下载
- 积分：1
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LAB-9
LAB 9, Excercise for DE2 Altera
- 2014-11-28 11:50:00下载
- 积分：1
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基于VHDL的RS232通讯程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用...
基于VHDL的RS232通讯程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-VHDL based on the RS232 communication procedures, including complete source code, locking pin, as well as download files documents can be directly downloaded using
- 2023-07-14 19:45:03下载
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processor
processor design istruction load pipeline ,hazard
- 2010-04-02 03:52:08下载
- 积分：1
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ISARCSSim_az
基于压缩感知的ISAR方位向成像以及与FFT成像对比(CS-based ISAR imaging and RD imaging)
- 2013-04-07 15:16:53下载
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Three
Three-input Majority Voter
-- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways.
-Three-input Majority Voter -- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways.
- 2022-08-12 06:51:37下载
- 积分：1
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一篇关于FIFO设计以及FPGA设计的文章
一篇关于FIFO设计以及FPGA设计的文章-FIFO 1 on the design and FPGA design article
- 2022-11-02 11:35:03下载
- 积分：1
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crc循环冗余校验码，用于对传输信号进行编码校验，是信息更可靠...
crc循环冗余校验码，用于对传输信号进行编码校验，是信息更可靠-crc cyclic redundancy check code used to transmit coded signals to verify, the information is more reliable
- 2022-12-26 06:05:03下载
- 积分：1
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spi_controller
SPI控制器，基于VERILOG描述，分模块设计，共6个模块，时钟产生模块，移位模块，主模块，从模块，定义模块，顶层模块。(SPI controller, based on the VERILOG description, sub-module design, a total of six modules, clock generation module, shift module, main module, from the modules, custom module, top module.)
- 2021-05-13 13:30:02下载
- 积分：1
