-
用VHDL语言实现CPLD（EPM240T100C5组成）串口接收程序
利用VHDL实现CPLD（EPM240T100C5）的串口接收程序-Using VHDL realize CPLD (EPM240T100C5) the serial receive procedure
- 2022-05-20 12:04:11下载
- 积分：1
-
本文介绍了使用verilog语言进行硬件设计的一些基本技巧
本文介绍了使用verilog语言进行硬件设计的一些基本技巧-This paper describes the use of Verilog hardware design language, the basic skills
- 2022-04-08 11:38:23下载
- 积分：1
-
verilog-digital-system-design-
verilog数字系统设计，一本很好的verilog学习的书籍，很适合初学者(verilog digital system design, a good verilog learning books, it is suitable for beginners)
- 2021-01-10 20:28:50下载
- 积分：1
-
分别用分频比交错法及累加器分频法完成非整数分频器设计。...
分别用分频比交错法及累加器分频法完成非整数分频器设计。-Points were staggered method and frequency than the frequency accumulator law to complete the design of non-integer divider.
- 2022-01-25 23:28:15下载
- 积分：1
-
rscode
R S编 解 码 实 现 代 码
verilog语言(RS CODE AND ENCODE)
- 2013-05-19 16:19:55下载
- 积分：1
-
FFT_VHDl
VHDL实现快速傅里叶变换，内附带资料以及源代码。(VHDL fast Fourier transform, within the supplied data and source code.)
- 2020-08-14 20:08:27下载
- 积分：1
-
gam7
FPGA Implementation ofLow Power 64-Point
Radix-4 FFT Processor for OFDM System
- 2011-01-22 11:45:44下载
- 积分：1
-
lab6-3-8DECODER
数字设计和计算机体系结构：用verilog语言描述3-8译码器的设计与实现(Digital design and computer architecture: use verilog language describe 3-8 decoder design and implementation)
- 2016-10-24 17:20:07下载
- 积分：1
-
基于fpga和xinlinx ise的小游戏的vhdl程序，希望对你有所帮助！
基于fpga和xinlinx ise的小游戏的vhdl程序，希望对你有所帮助！-xinlinx and they simply based on the small game and ideally the VHDL process, and I hope to help you!
- 2022-03-13 03:44:13下载
- 积分：1
-
newViterbi217
基于IEEE802.11n标准,采用verilog语言设计的(2,1,7)卷积码viterbi译码器,支持1/2,2/3,3/4,5/6四种码率的译码,以测试无误(IEEE802.11n standard Verilog language design (2,1,7) convolutional code viterbi decoder support 1/2, 2/3, 3/4, 5/6 four bit rate decoding to test and correct)
- 2020-06-29 08:40:01下载
- 积分：1
