登录
首页 » VHDL » 占空比1:1的通用分频模块

占空比1:1的通用分频模块

于 2022-11-11 发布 文件大小:809.00 B
0 104
下载积分: 2 下载次数: 1

代码说明:

占空比1:1的通用分频模块-1:1 generic-frequency module

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 基于FPGA的多波形发生器 基于FPGA的多波形发生器
    基于FPGA的多波形发生器 基于FPGA的多波形发生器-FPGA-based multi-waveform generator based on multi-FPGA Waveform Generator
    2022-03-17 22:22:40下载
    积分:1
  • sp605_BRD_rdf0033_13.2_c
    spartan605评估板测试代码。xilinx官方资料(spartan605 uation board test code)
    2014-12-23 22:27:45下载
    积分:1
  • 实现LMS的VHDL代码。
    Implement LMS vhdl code.
    2022-07-11 07:46:06下载
    积分:1
  • 在quartus中使用IP核的实际例子与流程
    在quartus中使用IP核的实际例子与流程-The use of IP in the Quartus practical examples and nuclear flow
    2022-08-07 01:33:34下载
    积分:1
  • CAN总线开发代码 can-sja1000
    CAN总线开发代码,FPGA与sja1000通信,可实现CAN的接收和发送。(The FPGA and the sja1000 CAN bus development code, communication, which CAN realize the CAN send and receive.)
    2021-04-14 17:08:55下载
    积分:1
  • PWM
    采用STC89C52单片机的定时器以实现两路PWM波输出,占空比、频率可调(Microcontroller timer used to achieve STC89C52 two PWM wave output, duty cycle, frequency adjustable)
    2021-04-24 10:08:47下载
    积分:1
  • memristor
    忆阻器的PSPICE仿真,是忆阻器的宏模型,适合于cadence16.5版本(memristor PSPICE simulation)
    2021-02-20 09:39:43下载
    积分:1
  • 2003101190493221
    还好用,大家一起来看下,不错的图书管理软件啊 ,呵呵(Fortunately with, everyone look, the good library management software, ah, huh, huh)
    2010-09-14 13:08:40下载
    积分:1
  • CPU
    运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括:取指模块,译码模块,执行模块,访存模块,写回模块,寄存器组模块,控制相关检测模块,Forwarding模块。该CPU在TEC-CA实验平台上运行,并且通过Debugcontroller软件进行单步调试,实验表明,该流水线CPU消除了控制相关、数据相关和结构相关。(Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related.)
    2020-09-21 10:37:53下载
    积分:1
  • goodProcessor.srcs
    说明:  处理器系统,处理器加上存储器,从存储器取出指令放入处理器执行(processor system, instructions stored in ROM, a counter generate address and the processor execute instructions.)
    2020-10-10 23:10:02下载
    积分:1
  • 696518资源总数
  • 105547会员总数
  • 4今日下载