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mc8051内核,VHDL程序,内有说明,超详细.
mc8051内核,VHDL程序,内有说明,超详细.-mc8051 kernel, VHDL program, which has made it clear, super-detailed.
- 2022-07-04 05:44:07下载
- 积分：1
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A4_Oscilloscope_Top
说明： 数字示波器实验，利用AD、DA和VGA三个外设来实现简易示波器，DA外设发送正弦波给AD外设，AD外设解析成数字信号将数据送给VGA外设进行显示。在VGA上可以看到DA外设发送的波形、波形频率和波形峰峰值。(In the experiment of digital oscilloscope, AD, DA and VGA are used to realize simple oscilloscope. DA peripheral transmits sine wave to AD peripheral. AD peripheral resolves into digital signal and sends data to VGA peripheral for display. The waveform, waveform frequency and peak value of DA peripheral can be seen on VGA.)
- 2019-03-13 10:45:10下载
- 积分：1
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single_phase_inverter_wangyafankui
带有电网电压反馈的单相PWM整流器反馈，输出的波形很好，适合初学者学习观摩(With power grid voltage feedback single-phase PWM rectifier feedback, the output waveform is very good, suitable for beginners learning view
)
- 2012-11-30 16:16:04下载
- 积分：1
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lm016液晶的VHDL代码
应用背景这是lm016液晶的VHDL代码。lm016液晶显示器基本上由2行和2列组成。有2种类型接口，8）1位接口2）4位接口在这个包中给出了8位接口代码因为它很容易，但唯一的缺点是，它使用了更多的引脚数据和指令传输。关键技术此代码是 测试；FPGA开发板–xc6slx9-tqg144斯巴达6注意：液晶显示器引脚数字引脚47液晶使能引脚数字引脚50LCD RW引脚数字引脚48LCD D0引脚数字引脚51液晶D1引脚数字引脚55LCD D2引脚数字引脚56LCD D3引脚数字引脚57LCD D4引脚数字引脚58LCD D5引脚数字引脚59LCD D6引脚数字引脚61液晶D7引脚数字引脚62
- 2022-03-13 00:00:48下载
- 积分：1
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fpga_sdram_inst
nios学习资料，fpga调用外部sdram实例，值得初学者下载。(nios learning materials, fpga call external sdram instance, it is worth beginners to download.)
- 2013-08-24 22:26:31下载
- 积分：1
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数字频率计
设计一简易数字频率计，其基本要求是：
1)测量频率范围0～999999Hz；
2)最大读数999999HZ,闸门信号的采样时间为1s；.
3)被测信号可以是正弦波、三角波和方波；
4)显示方式为6位十进制数显示；
5）具有超过量程报警功能。
5)输入信号最大幅值可扩展。
6）测量误差小于+-0.1%。
7)完成全部设计后，可使用EWB进行仿真，检测试验设计电路的正确性。(The basic requirements of designing a simple digital frequency meter are:
1) The measuring frequency range is 0-999999 Hz.
2) The maximum reading is 999999HZ, and the sampling time of gate signal is 1 s.
3) The measured signal can be sine wave, triangle wave and square wave.
4) The display mode is 6-bit decimal number display.
5) It has alarm function beyond range.
5) The maximum amplitude of input signal can be expanded.
6) The measurement error is less than +0.1%.
7) After completing all the design, EWB can be used to simulate and test the correctness of the circuit.)
- 2019-06-20 12:47:51下载
- 积分：1
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Motor Control PWM wave generated by the procedure, VHDL language
电机控制中PWM波产生的程序，VHDL语言实现-Motor Control PWM wave generated by the procedure, VHDL language
- 2022-07-10 02:37:51下载
- 积分：1
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pipeline_FPGA
FPGA流水线设计的资料，可以作为学习FPGA开发并行操作的一个经典教材，具有很好的指导作用。(FPGA pipeline design information can be developed as a learning FPGA parallel operation of a classic textbook, has a good guide.)
- 2011-07-02 12:00:57下载
- 积分：1
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用Verlog HDL编写的数字钟程序，包含时，分，秒，进位，解码，扫描显示等功能。...
用Verlog HDL编写的数字钟程序，包含时，分，秒，进位，解码，扫描显示等功能。-Written by Verlog HDL ，a digital clock program, including hours, minutes, seconds, into the place, decoding, scanning display.
- 2023-02-05 04:55:03下载
- 积分：1
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四位动态刷新数码管显示，ＶＥＲＩＬＯＧ代码，含详细的中文注释．...
四位动态刷新数码管显示，ＶＥＲＩＬＯＧ代码，含详细的中文注释．-Four dynamic refresh digital tube display, VERILOG code, with detailed notes in Chinese.
- 2022-02-10 00:53:27下载
- 积分：1
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