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turbo[1].tar
turbo码的verilog程序,有意者请下载。(turbo code verilog procedures Interested parties please download.)
- 2021-01-14 17:58:46下载
- 积分:1
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fft64
verilog hdl 编写的64点fft代码,适合很多芯片(coded by verilog hdl that implement 64 point fft, suite to many core)
- 2020-12-12 21:19:16下载
- 积分:1
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脉冲多普勒雷达回波信号相干积累的VHDL源程序
脉冲多普勒雷达回波信号相干积累的VHDL源程序-pulse Doppler radar echo signal coherent accumulation of VHDL source
- 2022-12-08 18:50:02下载
- 积分:1
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picorv32-master
说明: PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt controller.
Tools (gcc, binutils, etc..) can be obtained via the RISC-V Website. The examples bundled with PicoRV32 expect various RV32 toolchains to be installed in /opt/riscv32i[m][c]. See the build instructions below for details.
- 2020-06-24 21:40:01下载
- 积分:1
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FPGASquare-RootRaised-CosineFilter
数字通信系统中, 基带信号的频谱一般较宽, 因此
传递前需对信号进行成形处理, 以改善其频谱特性,使
得在消除码间干扰与达到最佳检测接收的前提下,提高信道的频带利用率。目前,数字系统中常使用的波形成形滤波器有平方根升余弦滤波器、 高斯滤波器等。设计方法有卷积法或查表法, 其中: 卷积法的实现,需要消耗大量的乘法器与加法器,以构成具有一定延时的流水线结构。为降低硬件消耗,文献提出了一种分(FPGA Implementation of Square Root Raised Cosine Pulse Shaping Filter)
- 2011-05-04 21:23:36下载
- 积分:1
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一个用VerilogHDL语言编写的模6的二进制计数器
一个用VerilogHDL语言编写的模6的二进制计数器-a Verilog HDL language used in the preparation of the six-binary counter
- 2022-03-22 05:41:51下载
- 积分:1
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shiyan5
应用布莱克曼窗实现FIR滤波器,并绘制相应波形图案(Application Blackman window FIR filter, and draw the corresponding waveform pattern)
- 2014-01-09 11:50:49下载
- 积分:1
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Source code for asyn_fifo using verilog language.
异步FIFO 设计源代码,内涵完整的verilog源代码和测试代码。-Source code for asyn_fifo using verilog language.
- 2022-04-14 15:20:53下载
- 积分:1
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CPU-master
说明: misp,五级流水源码,实现一个建议的cpu(Misp, five-stage flow source code, implementation of a recommended CPU)
- 2020-06-16 00:00:07下载
- 积分:1
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55593402DDS_vhdl
DDS分频实现,全部代码的完整过程,包括截图等(DDS divider to achieve the complete process of all the code)
- 2013-05-15 16:49:55下载
- 积分:1