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dds_test
说明： 直接数字式频率合成器DDS设计、Verilog。
产生的信号可以是正弦波或方波、三角波、锯齿波等，自选。
采用DDS技术，将所需生成的波形写入ROM中，按照相位累加原理合成任意波形。
此方案得到的波形稳定，精度高，产生波形频率范围大，容易产生高频。
本实验在设计的模块中，包含以下功能：
（1）通过 freq 信号输入需要的频率的值；
（2）通过 wave_sel 信号选择所需的波形；
（3）通过 amp_adj 信号选择波形放大的倍数。(DDS design of direct digital frequency synthesizer, Verilog.
The generated signal can be sinusoidal or square wave, triangular wave, sawtooth wave and so on, optional.
By using DDS technology, the required waveforms are written into ROM, and arbitrary waveforms are synthesized according to the principle of phase accumulation.
The waveform obtained by this scheme is stable, accurate and easy to generate high frequency waveform.
This experiment includes the following functions in the designed module:
(1) Input the required frequency value through freq signal;
(2) Choosing the required waveform by wave_sel signal;
(3) Select the multiplier of waveform amplification by amp_adj signal.)
- 2019-01-19 16:07:50下载
- 积分：1
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PLD与8051接口的参考设计 Xilinx提供的verilog源代码
PLD与8051接口的参考设计 Xilinx提供的verilog源代码-PLD 8051 interface with the Xilinx Reference Design for the Verilog source code
- 2022-05-12 14:58:28下载
- 积分：1
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modulation-and-demodulation
通过verilog语言实现各种基本信号的调制解调过程，包括2psk,qpsk,ppm(Realize the modulation and demodulation process of various basic signals through verilog language, including 2psk, qpsk, ppm)
- 2018-04-26 21:52:04下载
- 积分：1
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读写FAT32文件系统的SD卡实验
资源描述该程序可以读写FAT32文件系统的SD卡。SD卡的接口现在采用IO模拟接口方式。在板子SD卡座上插上FAT32格式的SD卡，请连接下载线的JTAG接口到板子，下载fpga的SOF文件，再下载NIOSII IDE中的文件。
- 2022-02-09 20:27:01下载
- 积分：1
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Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0],...
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
- 2022-04-13 06:40:15下载
- 积分：1
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quartus2
quartus2的中文文档，不是很全，仅供大家学习(quartus2 the Chinese document, not very wide, only for them to learn)
- 2010-07-29 19:49:52下载
- 积分：1
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液晶的控制，有VHDL语言实现
液晶的控制，有VHDL语言实现-lcd control
- 2022-03-23 07:01:23下载
- 积分：1
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上海大学 Verilog PPT 适合初学者看 推荐
上海大学 Verilog PPT 适合初学者看 推荐 -Shanghai University Verilog PPT look recommended for beginners
- 2022-04-19 13:38:15下载
- 积分：1
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jk-filpflop
这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)
- 2013-11-19 11:43:07下载
- 积分：1
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串口中断＿niosII.rar
解压密码：www.21control.com
串口中断＿niosII.rar
解压密码：www.21control.com
- 2023-01-05 21:10:04下载
- 积分：1
