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jianpan
说明： 一个简单的键盘接口模块程序，对键盘输入的数据和时钟信号进行过滤。过滤后的数据信号PS2Df将被送入两个11位移位寄存器中(A simple keyboard interface module program filters keyboard input data and clock signals. The filtered data signal PS2Df will be fed into two 11-bit displacement registers.)
- 2020-06-24 02:00:02下载
- 积分：1
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single_phase_inverter_wangyafankui
带有电网电压反馈的单相PWM整流器反馈，输出的波形很好，适合初学者学习观摩(With power grid voltage feedback single-phase PWM rectifier feedback, the output waveform is very good, suitable for beginners learning view
)
- 2012-11-30 16:16:04下载
- 积分：1
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HDMI接口编解码传输模块ASIC设计_刘文杰
? 熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。
? 利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。
? 利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。
? 利用双线性插值方法实现对图像640×480到1024×768的放大操作。
? 完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format.
Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface.
With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA.
The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768.
Complete the VGA display interface design.)
- 2020-06-25 04:00:02下载
- 积分：1
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7-segment
VHDL Design of BCD to 7-segment decoder
using PROM
- 2009-05-04 02:44:02下载
- 积分：1
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基于VHDL的1602显示程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用
基于VHDL的1602显示程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-VHDL-based display program in 1602, contains the complete source code, locking pin, as well as download files documents can be directly downloaded using
- 2023-06-18 04:20:03下载
- 积分：1
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verilog
一些简单的Verilog代码，小例程，比如求平均值、七段数码管等等(Some simple Verilog code, small routines, such as averaging, seven digital tubes and so on)
- 2016-12-12 10:02:20下载
- 积分：1
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Hardware-CNN-master
Convolutional neural network code for fpga
- 2019-02-27 15:21:22下载
- 积分：1
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fifo
fifo的代码,经过测试可以使用，很有用处，可以放心使用(a fifo module,the code has been tested and it is usefull)
- 2010-03-02 22:03:30下载
- 积分：1
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FPGA下PWM的Verilog 源码，含目标程序，可直接下载使用，可用在电机控制中...
FPGA下PWM的Verilog 源码，含目标程序，可直接下载使用，可用在电机控制中-FPGA in Verilog source code under the PWM, including the target program, can be directly downloaded to use, can be used in motor control in
- 2022-07-04 10:40:23下载
- 积分：1
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verilog HDL 写的LMS滤波器
verilog HDL 写的LMS滤波器-LMS filter using verilog HDL language
- 2022-05-28 16:08:42下载
- 积分：1
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