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weifen-program
基于FPGA微分程序代码及其电路驱动程序(Based on FPGA differential program
)
- 2011-12-19 12:17:59下载
- 积分：1
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verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，9...
verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，9-10章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 9-10
- 2022-08-15 23:59:39下载
- 积分：1
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VHDL实现快速傅立叶变换
VHDL实现快速傅立叶变换 -VHDL implementation VHDL implementation of Fast Fourier Transform Fast Fourier Transform
- 2022-06-14 14:36:57下载
- 积分：1
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AM-800480SBTMQW-TW0-pdf
800 x 480 / inch lcd
- 2013-01-15 21:43:46下载
- 积分：1
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程序采用VHDL：频率合成DDS主要调用LPM，
程序用VHDL实现：
频率合成，DDS
主要调用LPM-procedures using VHDL : frequency synthesis, DDS major call LPM
- 2023-07-07 03:20:03下载
- 积分：1
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VHDL language used to write the VGA control procedures have been verified, the a...
用VHDL语言写的VGA 控制程序，已经验证过，绝对好用！-VHDL language used to write the VGA control procedures have been verified, the absolute ease of use!
- 2022-01-23 11:20:28下载
- 积分：1
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chuankou
说明： 本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)
- 2020-06-24 01:40:02下载
- 积分：1
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Interfacing_RTC_with_Spartan-3_Primer_FPGA
Interfacing RTC with spartan 3
- 2013-04-04 10:13:44下载
- 积分：1
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电梯
利用verilog编写的电梯程序，实现基本的电梯运行功能(Elevator program written by Verilog)
- 2018-11-25 11:39:50下载
- 积分：1
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软I2C
i2c硬件程序,字节读、字节写，在modelsim6.0通过编译-the soft for i2c
- 2022-09-15 23:15:03下载
- 积分：1
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