-
FPGA
基于FPGA与LM4550B的AC97软声卡VHDL语言驱动，版本2.0-FPGA-based soft and LM4550B the AC97 sound card driver VHDL language, version 2.0
- 2022-10-28 20:25:03下载
- 积分：1
-
AD7606URAT
Verilog实现高速AD7606数据采样，8通道，采样频率可调，支持串口数据发送，亲测可用。(Verilog AD7606 high-speed data sampling, 8-channel, the sampling frequency is adjustable, support for serial data transmission, pro-test is available.)
- 2021-04-16 21:38:53下载
- 积分：1
-
adder16b
说明： 潘松那本书上用vhdl语言描述的16位并入并处加法器(Pan book vhdl language used to describe the 16-bit adder into his)
- 2009-07-23 17:02:22下载
- 积分：1
-
tsobbellh
这是我本人自己开发的可用于256*256大小的图像进行sobel边缘检测的vhd文件，可在QuartusII或MaxplisII下综合与与仿真，并在FPGA上测试过。能进行修改支持其他大小图像的sobeel边缘检测，同时还能实现其它的图像模块化处理算法，例如高斯滤波，平滑等。
(This is my own development vhd file, can be used for 256* 256 size image sobel edge detection under QuartusII or MaxplisII synthesis and with simulation, and tested on FPGA. Can be modified to support other sobeel size image edge detection, while still achieving other image the modular processing algorithms, such as Gaussian filtering and smoothing.)
- 2012-08-23 22:17:19下载
- 积分：1
-
出租车模块设计加nios2设计cup程序代码
出租车模块设计加nios2设计cup程序代码...
出租车模块设计加nios2设计cup程序代码
出租车模块设计加nios2设计cup程序代码-Taxi modular design design cup plus nios2 code taxi modular design design cup plus nios2 code
- 2022-03-06 17:30:37下载
- 积分：1
-
FPGA_AD7822
基于FPGA的AD转换控制器设计，AD7822，quartus II，verilog hdl(A Design of the A/D Convertion Control Module Based on FPGA)
- 2011-08-26 15:06:18下载
- 积分：1
-
these files are written in verilog but i am uploading in text format
these files are written in verilog but i am uploading in text format
- 2022-01-26 00:53:26下载
- 积分：1
-
data_rom
正弦信号发生器，用VHDL来完成，抗干扰能力较强，(Sinusoidal signal generator, using VHDL to accomplish, a strong anti-interference ability,)
- 2009-07-15 22:44:02下载
- 积分：1
-
Viterberi 解码器
Viterberi 解码器使用 vhdl 编程实现将被用于制作增强功能
- 2023-03-06 21:00:04下载
- 积分：1
-
ADc
与单片机相比，用CPLD/FPGA器件更适合于直接对高速AD采样控制。本实验接口器件为ADC0809，根据ADC0809的工作时序使用CPLD产生该控制信号，CPLD启动AD转换后，得到的数据送至单片机并在PC机及数码管上显示AD转换结果。(Compared with the microcontroller, CPLD/FPGA devices more suitable for direct sampling control of high-speed AD. The interface of the experimental device for the ADC0809 ADC0809 Timing CPLD is used to generate the control signal, the CPLD to start the AD conversion, the data sent to the microcontroller and the AD conversion result on the PC and digital tube display)
- 2021-03-29 11:19:10下载
- 积分：1
