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一个可编程的间隔定时器的设计，8253要完成的功能，实…
设计一个可编程间隔定时器，完成8253的功能，实现以下几点要求：
1、 含有3个独立的16位计数器，能够进行3个16位的独立计数。
2、 每一种计数器具有六种工作模式。
3、 能进行二进制/十进制减法计数。
4、 可作定时器或计数器。
-The design of a programmable interval timer, 8253 to complete the function, realize the following requirements: 1, contains three independent 16-bit counter, capable of three independent 16-bit count. 2, each with six counter mode. 3, can be binary/decimal subtraction count. 4, can be used for the timer or counter.
- 2022-08-20 11:53:35下载
- 积分：1
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XilinxFpgaDesignAndTest
Xilinx fpga 设计培训中文教程,比较好的学习FPGA入门的教程(Xilinx fpga design training for Chinese curricula, better start learning FPGA Tutorial)
- 2020-08-13 15:58:30下载
- 积分：1
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VHDLcoding
本文件时VHDL的各种编写规范，有助于开发者在平时养成好的编码习惯(This document, the various write VHDL specification, helps developers to develop good coding habits in peacetime)
- 2009-11-20 11:44:58下载
- 积分：1
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inc_pid
基于FPGA的增量式PID设计方法，Matlab、Simulink， Xilinx Block set(Incremental PID FPGA-based design methodology)
- 2014-11-03 04:16:19下载
- 积分：1
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MVB_test
此功能是实现曼彻斯特编码的Verilog代码，经过在xilinx sp6上实际运行证实可行。(This function is to achieve the Manchester code Verilog code, through the Xilinx SP6 actual operation proved.)
- 2021-01-03 17:48:56下载
- 积分：1
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HDL的例子源代码2 / 5
HDL example source code 2/5
dff_en
- 2022-03-11 07:20:08下载
- 积分：1
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verilog例子资源，对于初学者很有帮助。
verilog例子资源，对于初学者很有帮助。-verilog examples of resources are very useful for beginners.
- 2023-08-15 15:30:03下载
- 积分：1
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pl_read_write_ps_ddr
说明： PL 和 PS 的高效交互是 zynq 7000 soc 开发的重中之重，常常需要将 PL 端的大量数据实时送到 PS 端处理，或者将 PS 端处理结果实时送到 PL 端处理，但是各种协议非常麻烦，灵活性也比较差，直接通过 AXI 总线来读写 PS 端 ddr 的数据，这里面涉及到 AXI4 协议，vivado 的 FPGA 调试等。(The efficient interaction between PL and PS is the top priority of zynq 7000 SoC development. We often need to send a large amount of data from PL to PS for real-time processing, or send the processing results from PS to pl for real-time processing. In general, we will think of using DMA for processing, but various protocols are very troublesome and the flexibility is poor. This course explains how to use Axi directly Bus to read and write DDR data of PS terminal, which involves axi4 protocol, FPGA debugging of vivado, etc.)
- 2021-01-22 17:46:44下载
- 积分：1
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用于FPGA的huffman算法的HDL编码
用于FPGA的huffman算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。(The huffman algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.)
- 2008-08-01 17:25:44下载
- 积分：1
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7段数码显示译码器
7段数码显示译码器-seven of the digital display decoder
- 2022-01-26 04:02:10下载
- 积分：1
