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基于ＦＰＧＡ平台，实现了直接数字频率合成。
基于ＦＰＧＡ平台，实现了直接数字频率合成。-FPGA-based platform, to achieve a direct digital frequency synthesis.
- 2022-03-01 23:16:21下载
- 积分：1
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对视频编解码芯片ADV7181进行合理的配置，使其输出符合ITUR656标准的视频流...
对视频编解码芯片ADV7181进行合理的配置，使其输出符合ITUR656标准的视频流-Of the ADV7181 video decoder chip for a reasonable configuration, so that the output in line with the standard video streaming ITUR656
- 2022-04-30 04:07:22下载
- 积分：1
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主要是通过Altera公司的Cuclone系列的FPGA
主要是通过Altera公司的Cuclone系列的FPGA-EP1C3T144C8产生余弦波的源代码 基于LPM-ROM余弦波一周期含有256个10位数据；-Mainly through Altera s Cuclone series of FPGA-EP1C3T144C8 cosine wave generated source code based on the LPM-ROM cosine wave of one cycle containing 256 10-bit data
- 2023-06-17 01:00:03下载
- 积分：1
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bin_to_bcd
VHDL之二進制轉BCD碼之程式碼，算完整的(Of binary to BCD code VHDL code, operator complete)
- 2013-03-13 16:05:11下载
- 积分：1
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Electric Guitar Digital Effects Processor
Electric Guitar Digital Effects Processor
- 2022-11-09 05:15:03下载
- 积分：1
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SPI
design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip’s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board. The sampling frequency is 20kHZ. Use a potentiometer.(design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip' s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board . The sampling frequency is 20kHZ. Use a potentiometer.)
- 2010-08-17 19:16:12下载
- 积分：1
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可重构 fir 滤波器 vhdl 代码
这是用 vhdl 语言编码的可重构的 fir 滤波器设计 fir 滤波器的实现代码
- 2022-06-13 16:25:01下载
- 积分：1
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usbd_ucos
说明： 基于ALINX AX7020硬件平台的USB-OTG通信程序。操作系统采用uCOS III v1.41，基本实现了双向USB2.0 块传输（Bulk Transfer）通信，zynq的PS端接收USB数据并回传至主机。经测试，主机端Window10系统采用libUSBK编程时，采用64字节的块时，传输速率可达210Mbps。zynq开发工具为Vivado2015.4，程序包中包含了全部的硬件和软件工程文档。(A USB-OTG communication project where an AX7020 platform is employed as USB device. The embeded operating system is uCOS III of version 1.41, and the FPGA toolchain is Vivado 2015.4. This project implements a full speed bidirectional USB2.0 bulk transfer. A test on Windows 10 host with libUSBK shows that the transfer speed is up to 201Mbps.)
- 2020-09-09 09:38:02下载
- 积分：1
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PID_Verilog
说明： PID算法用verilog语言实现，实测可用，由三个模块组成(The PID algorithm is implemented in Verilog language. The actual measurement is available. It consists of three modules.)
- 2019-04-30 02:32:21下载
- 积分：1
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在USB contreoller CRC5块
crc5 bolck in usb contreoller
- 2022-03-06 23:01:25下载
- 积分：1
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