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ds312_Spartan-3E-FPGA
FPGA资料与所用元器件的数据参考手册与应用指南(ds312_Spartan-3E FPGA Family )
- 2012-09-18 21:43:54下载
- 积分：1
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VGA count, PSW2 inverse control is counting? Reduced count, pop
VGA计数，PSW2控制正逆计数，按下递减计数，弹起正向计数。利用VGA作为输出设备，显示计数值。-VGA count, PSW2 inverse control is counting? Reduced count, pop-up being counted. The use of VGA as the output equipment, revealed count.
- 2022-04-17 09:49:34下载
- 积分：1
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FPGA
verilog编写的QPSK发射机的ＦＰＧＡ部分，已经过验证，完全达到要求。调制矢量误差４％(QPSK transmitter verilog prepared by the FPGA portion, has been proven, fully meet the requirements. Modulation vector error of 4 )
- 2013-10-08 14:58:23下载
- 积分：1
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fft变换三个中的一个（站长：三个代码算一个）
fft变换三个中的一个（站长：三个代码算一个）-one of the three fft transfermation code
- 2023-06-12 17:40:03下载
- 积分：1
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VHDL_COUNTING 与 4 使脉冲和使用 3 按钮了，下来，停止 （Mạch đếm với 4 xung ENA sử dụng 3 nút nhấn lên，xuống và dừng l
VHDL_COUNTING 与 4 使脉冲和使用 3 按钮了，下来，停止 （Mạch đếm với 4 xung ENA sử dụng 3 nút nhấn lên，xuống và dừng lại）
- 2022-03-19 05:46:27下载
- 积分：1
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within waveform generator, Adder, classic dual
内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
- 2023-09-02 09:40:03下载
- 积分：1
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weitb
在数字通信中，通常直接从接收到的数字信号中提取位同步信号，这种直接法按其提取同步信号的方式，大致可分为滤波法和锁相法。锁相法是指利用锁相环来提取位同步信号的方法，本设计方案就是基于锁相环的位同步提取方法，能够比较快速地提取位同步时钟，并且设计简单，方便修改参数。采用Quartus II设计软件对系统进行了仿真试验，并用Altera的Cyclone II系列FPGA芯片Ep2c5予以实现。(In digital communication, usually from receiving directly in digital signal extracted a synchronized signal, the direct method according to the extraction synchronized signal way, can be roughly divided into filtering method and phase lock method. Phase lock method is using of phase locked loop to extract a synchronized signal method, the design scheme is based on phase locked loop of a synchronous extraction method and can be quickly extract a synchronous clock, and design simple, convenient modification parameter. The Quartus II design software of the system, and the simulation test Altera Cyclone II FPGA chip to achieve Ep2c5 series.)
- 2020-12-01 10:39:28下载
- 积分：1
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Verilog-detail
不错的verilog学习语言资料，详细地对verilog语言中的重要语句应用进行分析。(A good the verilog learn language information, verilog language statement application.)
- 2013-03-26 13:01:23下载
- 积分：1
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vhdl经典源代码――键盘接口设计，入门者必须掌握
vhdl经典源代码――键盘接口设计，入门者必须掌握-vhdl classical source code-- the keyboard interface design, beginners must master
- 2022-11-20 22:55:03下载
- 积分：1
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-------
---- WISHBONE Wishbone_BFM IP Core----
--------
---- This file is par
---- ----
---- WISHBONE Wishbone_BFM IP Core ----
---- ----
---- This file is part of the Wishbone_BFM project ----
---- http://www.opencores.org/cores/Wishbone_BFM/ ----
---- ----
---- Description ----
---- Implementation of Wishbone_BFM IP core according to ----
---- Wishbone_BFM IP core specification document.---------
---- WISHBONE Wishbone_BFM IP Core----
--------
---- This file is part of the Wishbone_BFM project----
---- http://www.opencores.org/cores/Wishbone_BFM/----
--------
---- Description----
---- Implementation of Wishbone_BFM IP core according to----
---- Wishbone_BFM IP core specification document.
- 2022-05-26 15:36:06下载
- 积分：1
