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7×7交叉使用Verilog
这是Verilog代码使用Verilog实现交叉。
- 2022-10-06 06:25:03下载
- 积分:1
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Walsh
沃尔什函数序列sequency的verilog编程实现,含有测试文件(the Walsh sequence in sequency order)
- 2020-07-03 08:20:01下载
- 积分:1
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electrical lock
一个用Verilog写的电子锁工程,带testbench。(An electronic lock project written in Verilog with testbench.)
- 2020-06-30 05:00:01下载
- 积分:1
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同步
基于FPGA的位同步算法的verilog实现(Verilog implementation of synchronization algorithm)
- 2018-04-17 10:50:12下载
- 积分:1
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8_BUS
BUS documentation and map reffereces
- 2020-06-25 19:40:02下载
- 积分:1
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dingshi
定时器加数码管显示源码,以及test bench测试模块源码,经modelsim仿真结果正确(Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct)
- 2013-07-27 10:34:41下载
- 积分:1
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PS2_Core
or1200 PS2_Core code
- 2010-07-18 23:26:44下载
- 积分:1
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SDR
直接序列扩频通信的Verilog仿真代码,在Quartus II中实现。(Direct sequence spread spectrum communication Verilog simulation code, implemented in Quartus II.)
- 2011-01-16 12:18:18下载
- 积分:1
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blessing3.9.6
Blessing_3_v3_9_6稳定盈利set,仅限AUDNZD货币对,周期M1。
使用本压缩包内的SET,LAF默认是15,根据历史测试来看具有较大的风险,需要手动规避数据。
合理设置为LAF=8,请自行设置和调试,找到自己合适的风险值。
(Blessing_3_v3_9_6 stable profit set, only AUDNZD currency pairs, cycle M1.
Use this package in the SET, the default is 15 fans, according to the angles of history test has great risk, need to avoid data manually.
Reasonable set to fans = 8, please make your own setting and debugging, find their proper risk value.)
- 2015-04-15 22:45:03下载
- 积分:1
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stm8uart
Demo program for use UART STM8S
- 2013-09-05 03:18:35下载
- 积分:1