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7SegmenAngka
说明: asssembly ccode to turn on 7 segmen
- 2019-12-17 09:53:09下载
- 积分:1
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分别用分频比交错法及累加器分频法完成非整数分频器设计。...
分别用分频比交错法及累加器分频法完成非整数分频器设计。-Points were staggered method and frequency than the frequency accumulator law to complete the design of non-integer divider.
- 2022-01-25 23:28:15下载
- 积分:1
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Quadrature Deshifrator
这个
- 2022-06-29 04:52:15下载
- 积分:1
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PLL
FPGA板上的锁存器PLL控制代码(verilog代码)(FPGA board latch the PLL control code (Verilog code))
- 2021-03-19 17:29:19下载
- 积分:1
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chap12
《Verilog HDL 程序设计教程》9("Verilog HDL Design Guide" 9)
- 2007-07-01 16:33:31下载
- 积分:1
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sph-original-codes
SPH的原始代码,希望可以帮到大家啊关于模拟poiseuille的(simulate poiseuille fuild)
- 2020-10-22 10:27:23下载
- 积分:1
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xilinx 开发板程序,VGA控制显示
xilinx 开发板程序,VGA控制显示-Xilinx development board procedures, VGA display control
- 2022-03-29 02:35:53下载
- 积分:1
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软件开发环境:ISE 7.1i
仿真环境:ISE Simulator
1. 这个实例实现通过ISE Simulator工具实现一个具有两个方向共...
软件开发环境:ISE 7.1i
仿真环境:ISE Simulator
1. 这个实例实现通过ISE Simulator工具实现一个具有两个方向共八个灯的交通灯控制器;
2. 工程在project文件夹中,双击traffic.ise文件打开工程;
3. 源文件在rtl文件夹中,traffic.v为设计文件,traffic_tb.tbw是仿真波形文件;
4. 打开工程后,在工程浏览器中选择traffic_tb.tbw,在Process View中双击“Simulation Behavioral Model”选项,进行行为仿真,即可得到仿真结果。-Software development environment: ISE 7.1i simulation environment: ISE Simulator1. Realize this instance through the ISE Simulator tool to achieve a total of eight lights in both directions of traffic lights controller 2. Works project folder, double-click traffic.ise Open the project document 3. rtl source file in the folder, traffic.v for design documents, traffic_tb.tbw is the simulation waveform files 4. to open a project, the project browser, select traffic_tb.tbw, in the Process View in the double hit
- 2022-08-09 15:58:02下载
- 积分:1
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led_prj
spartan 3E和verilog HDL的初学者极好的教材,本程序可直接下载到spartan实验板上运行。(Spartan 3E and Verilog HDL beginners excellent materials, the program can be downloaded directly to the spartan experimental board run.)
- 2013-04-17 13:35:42下载
- 积分:1
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vhdl学习方法,含有大量的vhdl源代码,对vhdl的语法的介绍
vhdl学习方法,含有大量的vhdl源代码,对vhdl的语法的介绍-VHDL source习laugh Yang, Yi bleed at the nose cavity submerged stresses measured tungsten Daitou VHDL, VHDL-Qin Pang Yang cavity cavity Geng Zhuang
- 2023-07-17 16:40:03下载
- 积分:1