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testbench.sv
RS 编码和解码Verilog Code, 实现了RS（544,514)的编码和译码；(-RS Coding and Decoding Verilog code， implement RS（544,514))
- 2016-09-25 16:05:54下载
- 积分：1
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用VHDL语言编写的写存储器程序，可下载在FPGA中使用
用VHDL语言编写的写存储器程序，可下载在FPGA中使用-VHDL language used to write memory program can be downloaded in the FPGA using
- 2022-06-17 11:46:31下载
- 积分：1
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shuzishizhong
数字时钟，包括流程图以及编码和完整的实验报告，内容详细丰富。(Digital clock, including flowcharts, and coding and a full lab report, detailed and rich.)
- 2011-12-20 19:53:07下载
- 积分：1
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verilog HDL编写的出租车计费系统
verilog HDL编写的出租车计费系统-verilog HDL prepared Taxi Accounting System
- 2022-05-06 06:53:34下载
- 积分：1
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ozgul2013
Digital pre-distortion (DPD) is an advanced digital
signal-processing technique that mitigates the effects of power
amplifier (PA) nonlinearity in wireless transmitters. DPD plays
a key role in providing efficient radio digital front-end (DFE)
solutions for 3G/4G basestations and beyond. Modern FPGAs
are a promising target platform for the implementation of flexible
wireless DFE solutions, including DPD.
- 2019-01-05 18:20:30下载
- 积分：1
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32FIRVHDL
基于FPGA的32阶FIR数字滤波器设计 源程序。设计使用了并行乘法器，运行速度更快，占用内存更小，延迟更小。
(32 order FIR digital filter based on FPGA design source program. Design USES parallel multiplier, faster and less memory, less delay.)
- 2014-05-12 21:11:19下载
- 积分：1
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2位并行加法器初学者必看初步了解FPGA
2位并行加法器初学者必看初步了解FPGA-two count
- 2023-07-28 14:05:03下载
- 积分：1
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Verilog prepared using USB download cable program realize USB protocol and JTAG...
用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机-Verilog prepared using USB download cable program realize USB protocol and JTAG interface to achieve data conversion state machine
- 2022-01-26 07:07:00下载
- 积分：1
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VGA count, PSW2 inverse control is counting? Reduced count, pop
VGA计数，PSW2控制正逆计数，按下递减计数，弹起正向计数。利用VGA作为输出设备，显示计数值。-VGA count, PSW2 inverse control is counting? Reduced count, pop-up being counted. The use of VGA as the output equipment, revealed count.
- 2022-04-17 09:49:34下载
- 积分：1
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行人交通灯系统设计与7段显示
- 2022-08-09 10:50:36下载
- 积分：1
