-
CODE_VHDL_COUNTING 0 到 9 (慈 0 đến 9 Đếm hiển đoạn 施耐 1 带领 7)
CODE_VHDL_COUNTING 0 到 9 (慈 0 đến 9 Đếm hiển đoạn 施耐 1 带领 7)
- 2023-04-13 10:55:04下载
- 积分:1
-
FPGA+AD7656
说明: FPGA控制AD7656和模拟开关实现36路模拟量循环采集(FPGA control AD7656 and analog switch to realize 36 channels of analog cyclic acquisition)
- 2020-10-11 23:27:32下载
- 积分:1
-
AD9250 204b Verilog源码
说明: AD9250是一款双通道14位ADC,最高采样速率250 MSPS,JESD204B Subclass 0或Subclass 1编码串行数字输出(The ad9250 is a dual channel 14 bit ADC with a maximum sampling rate of 250 MSPs and jesd204b sub class 0 or sub class 1 coded serial digital output)
- 2021-04-14 11:01:55下载
- 积分:1
-
all passed, I was carefully designed, fully meet the requirements of beginners....
全部通过,是我的精心设计,完全满足初学者的要求。0-99自动记数-all passed, I was carefully designed, fully meet the requirements of beginners. 0-99 automatic counting
- 2022-05-05 06:11:20下载
- 积分:1
-
seg7
SEG7数码管显示示例程序,适用于ALTERA的CPLD(SEG7 digital display sample program of ALTERA CPLD)
- 2012-05-31 10:29:25下载
- 积分:1
-
VMD642_CPLD
本例程位于 VMD642_CPLD目录中。
使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使
用 Verilog HDL书写,编译开发系统使用 Cypress公司的 Warp 6.3。(This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.)
- 2013-09-13 13:59:52下载
- 积分:1
-
classdiagramnew
class diagram diagram for AIRS
- 2015-06-10 22:44:10下载
- 积分:1
-
抢答器仿真
本文件包括整个基于QuartusII实现的抢答器模块,其下包括各个分模块,实现效果较不错。
- 2022-08-10 14:21:30下载
- 积分:1
-
VHDL_programs
VHDL programmes for basic digital circuits. begineers can learn easily
- 2013-09-28 13:46:58下载
- 积分:1
-
TFT_CTRL_800_480_16bit
文件用于驱动TFT屏,分辨率800*400,平台为quartus13,芯片为cycloneIV(The file is used to drive the TFT screen with a resolution of 800*400. The platform is quartus 13 and the chip is cyclone IV.)
- 2019-04-12 09:22:29下载
- 积分:1