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SinglePeriodCPU
说明： verilog语言书写，单周期CPU源码(single period CPU)
- 2020-11-25 11:59:32下载
- 积分：1
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delta-sigma
实现了MASH111功能，输入位数可编程(MASH 1-1-1, delta-sigma , input bits are programmable)
- 2021-04-20 23:18:50下载
- 积分：1
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LVDS_SRC
实现LDVS接口数据接收 含有协议结构以及处理(lvds Verilog 512 frame)
- 2015-12-04 14:09:58下载
- 积分：1
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基于sopc ep2c5开发板的rs232例程
基于sopc ep2c5开发板的rs232例程-On sopc ep2c5 development board rs232 routines
- 2022-02-05 03:28:05下载
- 积分：1
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Ａ８２５５的ｖｈｄｌ源代码，比较简单的一个
Ａ８２５５的ｖｈｄｌ源代码，比较简单的一个-Vhdl source code of A8255
- 2022-05-07 14:31:39下载
- 积分：1
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3FP
一个三分频verilog模块，可以用来学习基本结构。(A three points frequency verilog module can be used to study the basic structure.)
- 2013-08-25 00:41:29下载
- 积分：1
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数字相位
PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
- 2023-05-28 08:00:03下载
- 积分：1
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BMD_PCIE
自己根据xapp1052修改的源代码，已经编译成功，并应用在开发板上。(According xapp1052 own modified source code has been successfully compiled and used in the development board.)
- 2015-10-19 08:10:20下载
- 积分：1
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reversible-squarer
it is hybrid squarer circuit which will be designed using reversible gates which having les hardware complexity with compared to the conventional gates
- 2015-04-21 15:05:54下载
- 积分：1
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PCIeData-Link-Layer-Specifications
PCIe数据链路层的协议详解，对做PCIe接口有非常重要的指导价值。(PCIe data link layer protocol detailed, do PCIe interface very important value.)
- 2012-08-31 12:33:15下载
- 积分：1
