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USB 1.1 IP
USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
- 2022-05-24 18:47:17下载
- 积分：1
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此示例是8051核加频率计的联合设计,带有8051IP核资料
此示例是8051核加频率计的联合设计,带有8051IP核资料-This example is the 8051 nuclear increase the frequency of joint design, with the nuclear information 8051IP
- 2022-06-14 22:57:42下载
- 积分：1
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project_1
说明： 简单的一个Verilog小程序，适合刚接触的人群(A simple Verilog small program, suitable for people just contact)
- 2020-06-16 22:20:01下载
- 积分：1
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4x4 electronic locks central control system. Six input control.
4X4电子密码锁的中央控制系统。控制6位输入。-4x4 electronic locks central control system. Six input control.
- 2022-02-10 10:06:12下载
- 积分：1
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FIFO
This is a simple example of FIFO(first in and first out) module written in verilog code(This is a simple example of FIFO (first in and first out) module written in verilog code)
- 2013-10-04 00:41:42下载
- 积分：1
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pluse
说明： 发送两个频段的脉冲 个数和频率均可调
发送两个频段的脉冲 个数和频率均可调(pluse and adjust the width of pluse pluse and adjust the width of pluse )
- 2010-04-14 11:00:03下载
- 积分：1
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Dec_mul
时间同步后即可确定每帧数据的起始位置，这样就能完整的截取下每一帧。但是，数据中还带有频偏信息。在常规的通信系统中，多普勒很小仅仅会带来很小的频偏，但是在大多普勒的情况下，频偏将非常大，20马赫的速度将会带来将近34K的频偏。因此，如何很好的纠正频偏即为本系统的难点。
OFDM中，我们将大于子载波间隔倍数的频偏称为整数倍频偏，而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔，频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想，由于硬件资源限制，我们将在接收端做64点FFT，即相当于将频域划分为64份，我们将小于 的频偏称为小数倍频偏，将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system.
OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)
- 2013-12-26 18:00:24下载
- 积分：1
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110819_1
基于sopc的lcd时钟，开发工具为nios ii和quartus ii9.0(Based on sopc the lcd clock, development tools for the nios ii and quartus ii9.0)
- 2011-08-22 10:28:50下载
- 积分：1
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CDCM6208_SPI
说明： 完成对cdcm6208的时钟芯片的配置，输出高频时钟(cdcm6208 cofigure using SPI interface)
- 2021-02-06 18:29:56下载
- 积分：1
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有业主从PCI PCI、PCI目标是开源的，是项目的发展。
内有一PCI 主 和PCI从，PCI TARGET 都是公开代码的，是工程文件，有仿真工程，使用说明。觉得好的就推荐一下。
本PCI_HOST目前支持：
1、 对目标PCI_T进行配置；
2、 对目标进行单周期读写；
3、 可以工作在33MHZ和66MHZ
4、 支持目标跟不上时插入最长10时钟的等待。
ALTERA的PCI竟然收费的！！！软件里面调试仿真了半天，终于调通了，到了下载就突然弹出窗口说包含了有限制的IP CORE，是限制使用的-There is a PCI from PCI proprietors, PCI TARGET is open source, is the project document, there is simulation project, for use. Feel good about the recommendation. The PCI_HOST currently supports: 1, on the target configuration PCI_T 2, on the target for single-cycle read and write 3, can work in the 33Mhz and 66MHZ 4, to support the goals behind to insert a maximum of 10 clock hours of waiting. ALTERA the PCI even charges! ! ! Inside simulation software debugging for a long time, and finally had transferred to the download on the sudden pop-up window that contains a limited IP CORE, is to restrict the use of
- 2022-06-15 03:52:50下载
- 积分：1
