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sync(shipintongbuxinhao)
基于QuartusII环境下以模块化的形式做成的视频复合同步信号。(QuartusII-based environment to create the form of modular composite video sync signal.)
- 2009-04-06 12:49:46下载
- 积分：1
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QDPSKvhd
说明： 基于quartusII的QDPSK调制解调vhdl程序。(Modulation and demodulation based quartusII of QDPSK vhdl program.)
- 2010-04-23 17:30:53下载
- 积分：1
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My-Simple-Specturm--Analyzer
基于LabVIEW FPGA的频谱估计与分析(the power spectrum estimation and analysis based on LabVIEW FPGA)
- 2013-11-13 08:45:40下载
- 积分：1
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Pipeline-2
Pipeline processor verilog components
- 2012-12-21 17:53:18下载
- 积分：1
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FP6182
说明： PF6182是一款很好的DC-DC同步降压IC。输出电压可调整，电流达2A。非常好用(PF6182 is a good DC-DC synchronous buck IC. Adjustable output voltage and current up to 2A. Very easy to use)
- 2011-03-16 10:26:05下载
- 积分：1
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H.264编解码的VHDL语言写的
这里描述的VHDL源代码由若干模块下的释放
- 2022-04-18 20:33:11下载
- 积分：1
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emif_tt
实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d(Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding function module control, the document contains graphics, and after the simulation waveform simulation testing procedures, operating environment quartus ii11.0, simulation environment mmodelsim se 6.5d)
- 2020-12-04 15:59:23下载
- 积分：1
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6264
6264是一种8K×8的静态存储器.SRAM 的典型芯片有2KB 的6116、8KB 的6264 以及32KB的62256,其中6264 芯片应用最为广泛.(6264 is the 62256 typical chip SRAM.SRAM a 8K* 8 with 2KB 6116, 8KB 6264 and 32KB 6264 chip, which is most widely used.
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- 2015-02-01 13:28:11下载
- 积分：1
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weitb
在数字通信中，通常直接从接收到的数字信号中提取位同步信号，这种直接法按其提取同步信号的方式，大致可分为滤波法和锁相法。锁相法是指利用锁相环来提取位同步信号的方法，本设计方案就是基于锁相环的位同步提取方法，能够比较快速地提取位同步时钟，并且设计简单，方便修改参数。采用Quartus II设计软件对系统进行了仿真试验，并用Altera的Cyclone II系列FPGA芯片Ep2c5予以实现。(In digital communication, usually from receiving directly in digital signal extracted a synchronized signal, the direct method according to the extraction synchronized signal way, can be roughly divided into filtering method and phase lock method. Phase lock method is using of phase locked loop to extract a synchronized signal method, the design scheme is based on phase locked loop of a synchronous extraction method and can be quickly extract a synchronous clock, and design simple, convenient modification parameter. The Quartus II design software of the system, and the simulation test Altera Cyclone II FPGA chip to achieve Ep2c5 series.)
- 2020-12-01 10:39:28下载
- 积分：1
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使用vhdl语言实现对led的控制，还有电路仿真
使用vhdl语言实现对led的控制，还有电路仿真-Using vhdl language implementation of the led control, as well as circuit simulation
- 2022-03-12 11:40:55下载
- 积分：1
