登录
首页 » VHDL » 此示例是8051核加频率计的联合设计,带有8051IP核资料

此示例是8051核加频率计的联合设计,带有8051IP核资料

于 2022-06-14 发布 文件大小:463.55 kB
0 144
下载积分: 2 下载次数: 1

代码说明:

此示例是8051核加频率计的联合设计,带有8051IP核资料-This example is the 8051 nuclear increase the frequency of joint design, with the nuclear information 8051IP

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 6
    说明:  4位数码扫描显示电路,我们控制一个七段LED需要8个输出端口;如果要输出四位十进制数,就需要32的输出端口,这将占用大量的端口资源。采用串行扫描显示,我们只需要8+4共12个端口即可。其原理是:用一个四位的输出端控制,某一时刻只选中其中的一个LED(输出为‘1’表示选中),八位的输出端将该LED所需要显示的值输出;然后四位的输出端值改变,选中下一个LED。这样依次类推。如果选择的频率很快,达到50Hz以上,由于人眼的视觉暂留效应,看起来就像4个LED同时显示。 设计一个程序,输入四个一位十进制数,用4个LED显示出来。CLK采用频率可调信号发生器,逐渐改变频率,观察扫描频率的改变对输出效果的影响。 输入:连续脉冲,逻辑开关;输出:七段LED。 (4 digital scanning display circuit, we need to control a seven-segment LED output port 8 If you want to output four decimal numbers, you need the output port 32, which will take up a lot of ports. Serial scans showed, we need only 8 of 12 ports can be+4. The principle is: the output of four with a control, a time to select only one LED (output 1 is selected), 8 output of the LED by the need to show the value of the output then The output value of the four changes, select the next LED. This and so on. If you select the frequency rapidly, reaching more than 50Hz, as the human eye s persistence of vision effect, looks like a 4 LED display simultaneously. Design a program, enter a decimal number four, with four LED display. CLK signal generator with adjustable frequency, gradually changing the frequency of observed changes in scan frequency effect on the output. Input: Continuous pulse, logic switches output: seven-segment LED.)
    2010-06-21 22:07:59下载
    积分:1
  • relay_test
    Simple relay trigger
    2015-01-28 12:16:35下载
    积分:1
  • MTD_MTI
    (1)MTI (2)用FFT实现MTD (3)用FIR滤波器实现MTD ((1) MTI (2) using FFT realization MTD (3) with the FIR filter implementation MTD)
    2020-11-04 16:39:52下载
    积分:1
  • A4_Oscilloscope_Top
    说明:  数字示波器实验,利用AD、DA和VGA三个外设来实现简易示波器,DA外设发送正弦波给AD外设,AD外设解析成数字信号将数据送给VGA外设进行显示。在VGA上可以看到DA外设发送的波形、波形频率和波形峰峰值。(In the experiment of digital oscilloscope, AD, DA and VGA are used to realize simple oscilloscope. DA peripheral transmits sine wave to AD peripheral. AD peripheral resolves into digital signal and sends data to VGA peripheral for display. The waveform, waveform frequency and peak value of DA peripheral can be seen on VGA.)
    2019-03-13 10:45:10下载
    积分:1
  • uart_test
    verilog实现UART收发功能,硬件平台为spartan 6,软件平台为ise14.7(verilog implement UART rx and tx function)
    2017-10-07 16:34:13下载
    积分:1
  • fpga_security
    The use of FPGAs for cryptographic applications is highly attractive for a variety of reasons but at the same time there are many open issues related to the general security of FPGAs. This contribution attempts to provide a state-of-the-art description of this topic. First, the advantages of reconfigurable hardware for cryptographic applications are discussed from a systems perspective. Second, potential security problems of FPGAs are described in detail, followed by a proposal of a some countermeasure. Third, a list of open research problems is provided. Even though there have been many contributions dealing with the algorithmic aspects of cryptographic schemes implemented on FPGAs, this contribution appears to be the first comprehensive treatment of system and security aspects.
    2009-05-15 07:09:06下载
    积分:1
  • write VHDL 8051 kernel, available, convenient, can be downloaded interested in t...
    VHDL写的8051内核,可用的,好用,有兴趣可下载,在外国网站下载的-write VHDL 8051 kernel, available, convenient, can be downloaded interested in the foreign website
    2022-01-25 17:39:39下载
    积分:1
  • CPU-Verilog
    简单流水线CPU,使用 verilog实现,实现一条指令的整个流程(Implementation of Simple Pipeline CPU Verilog)
    2020-06-23 19:40:01下载
    积分:1
  • 基于FPGA的红外图像预处理系统的研究与设计,给fpga工程技术人员一个参考...
    基于FPGA的红外图像预处理系统的研究与设计,给fpga工程技术人员一个参考-FPGA-based infrared image preprocessing system and design, engineering and technical personnel to fpga a reference
    2023-06-10 21:00:04下载
    积分:1
  • ddr2_controller
    DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.(DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.)
    2010-02-23 09:16:50下载
    积分:1
  • 696518资源总数
  • 106245会员总数
  • 18今日下载