登录
首页 » VHDL » 有业主从PCI PCI、PCI目标是开源的,是项目的发展。

有业主从PCI PCI、PCI目标是开源的,是项目的发展。

于 2022-06-15 发布 文件大小:2.59 MB
0 151
下载积分: 2 下载次数: 1

代码说明:

内有一PCI 主 和PCI从,PCI TARGET 都是公开代码的,是工程文件,有仿真工程,使用说明。觉得好的就推荐一下。 本PCI_HOST目前支持: 1、 对目标PCI_T进行配置; 2、 对目标进行单周期读写; 3、 可以工作在33MHZ和66MHZ 4、 支持目标跟不上时插入最长10时钟的等待。 ALTERA的PCI竟然收费的!!!软件里面调试仿真了半天,终于调通了,到了下载就突然弹出窗口说包含了有限制的IP CORE,是限制使用的-There is a PCI from PCI proprietors, PCI TARGET is open source, is the project document, there is simulation project, for use. Feel good about the recommendation. The PCI_HOST currently supports: 1, on the target configuration PCI_T 2, on the target for single-cycle read and write 3, can work in the 33Mhz and 66MHZ 4, to support the goals behind to insert a maximum of 10 clock hours of waiting. ALTERA the PCI even charges! ! ! Inside simulation software debugging for a long time, and finally had transferred to the download on the sudden pop-up window that contains a limited IP CORE, is to restrict the use of

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • UART
    基于FPGA设计的串口发送及接收程序,波特率可调(FPGA - based serial port sending and receiving)
    2020-06-18 23:20:01下载
    积分:1
  • verilog hdl verilog hdl verilog hdl
    verilog hdl verilog hdl verilog hdl-verilog hdl
    2022-07-23 23:39:39下载
    积分:1
  • encode_64_66
    自编的64B/66B编码程序,下次上传解码程序。(the 64B/66B coding process is written by myself, i will upload the decoding process next time.)
    2011-08-27 10:38:53下载
    积分:1
  • for Dictyophora board, in the way of achieving LCD clock function.
    适合DE2板,能够在板子上的液晶显示器上实现时钟功能。-for Dictyophora board, in the way of achieving LCD clock function.
    2023-08-10 07:45:03下载
    积分:1
  • 欢迎大家使用该程序,是在FPGA下使用开发的。请大家使用。
    欢迎大家使用该程序,是在FPGA下使用开发的。请大家使用。-Welcome to use the program is to use FPGA development. Please use the.
    2022-06-19 03:41:34下载
    积分:1
  • PiSo
    8位并行输入的数转换成串行输出,是基于高级硬件编程语言VHDL编写的。(8-bit parallel input into serial output digital conversion is based on the high-level hardware programming language VHDL prepared.)
    2020-11-30 21:59:27下载
    积分:1
  • hgfdg
    Quartus? II 相关的语言 详细介绍了VHDL verilog软件开发过程(Quartus ? II related language detailed introduces the verilog VHDL software development process )
    2011-07-31 00:24:42下载
    积分:1
  • fir_filter
    LOW pass FIR filter for multirate processing
    2015-02-09 09:59:02下载
    积分:1
  • 北斗定位系统卫星下行信号的基带处理部BDSSS-Transmie
    北斗定位系统卫星下行信号的基带处理部分——基于FPGA的的直接序列扩频发射机的设计与仿真。,已通过测试。 (Beidou positioning system satellite downlink signal baseband part- based on the design and simulation of the FPGA direct sequence spread spectrum transmitter. , Has been tested.)
    2012-10-04 00:05:36下载
    积分:1
  • Nios_Example_07_SD_35TFT
    这是一个nios工程,控制TFT液晶屏的程序。FPGA平台用Verilog HDL语言编写的,MCU软核程序有C语言编写。通过这一个完成的工程,你就会明白SOPC的一些实现方法。(This is a nios engineering, control TFT LCD screen program. The FPGA platform Verilog HDL language preparation with the nuclear program has a soft, MCU written in C language. Through this a complete project, you will understand some of the SOPC methods of realization. )
    2011-05-24 16:56:27下载
    积分:1
  • 696516资源总数
  • 106571会员总数
  • 2今日下载