-
tcoug
Synopsys®
Timing Constraints and Optimization
User Guide
- 2014-08-23 17:37:56下载
- 积分：1
-
Srikanth Vijayaraghavan
Srikanth Vijayaraghavan - A Practical Guide for SystemVerilog Assertions-Srikanth Vijayaraghavan- A Practical Guide for SystemVerilog Assertions
- 2022-05-29 04:08:08下载
- 积分：1
-
fftshixian
基于FPGA编写的verilog代码，在xilinx上仿真实现FFT变换(FPGA-based verilog code written in xilinx FFT transform Simulation)
- 2015-04-05 11:42:08下载
- 积分：1
-
Mano-CPU_VHDL-Implementation
Mano s cpu for Man s instructions
- 2012-04-28 01:04:57下载
- 积分：1
-
54948739-Digital-Signal-Processing-With-Field-Pro
I am in need of some codes of HDL
- 2014-02-10 22:18:48下载
- 积分：1
-
Dc to use a very good book a very good use of books dc
一个非常好的dc使用书籍
一个非常好的dc使用书籍-Dc to use a very good book a very good use of books dc
- 2022-03-02 00:03:36下载
- 积分：1
-
5408A
The SPFD5408A, a 262144-color System-on-Chip (SoC) driver
LSI designed for small and medium sizes of TFT LCD display, is
capable of supporting up to 240xRGBx320 in resolution which can
be achieved by the designated RAM for graphic data. The
720-channel source driver has true 6-bit resolution, which
(The SPFD5408A, a 262144-color System-on-Chip (SoC) driver
LSI designed for small and medium sizes of TFT LCD display, is
capable of supporting up to 240xRGBx320 in resolution which can
be achieved by the designated RAM for graphic data. The
)
- 2012-07-16 17:09:15下载
- 积分：1
-
随机数发生器
随机数发生器
- 2023-04-30 09:25:03下载
- 积分：1
-
Fractional_Time_Delay
Used for Time shifting discrete signals, it can do both integral and fractional sampling period delay. Original.
- 2020-12-16 22:29:12下载
- 积分：1
-
AVR_Core.tar
CPLD例程(语言)《Verilog HDL数字控制系统设计实例》AVR_Core.tar.gz-.rar(CPLDprogram dialogue /Verilog language design examples)
- 2011-11-12 20:43:49下载
- 积分：1
