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正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过...
正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-sine wave in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
- 2023-07-26 10:55:02下载
- 积分：1
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PulseWidth_detector_VHDL
通信控制中常用的脉冲宽度检测程序，VHDL模块化编成实现（原创）(communication control used in pulse width detection procedures, VHDL modular organization to achieve (original))
- 2007-03-28 17:41:46下载
- 积分：1
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SimpleVOut-master
SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals
in various formats. The cores connect using AXI-streams. Most configurations
(resolution, framerate, colordepth, etc.) are set at compile-time using
Verilog parameters. See svo_defines.vh for details on those parameters.
- 2020-06-24 21:20:01下载
- 积分：1
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04_uart_test
说明： 基于FPGA的串口发送和接收，使用的verlilog语言(Using Verilog serial port program, send and receive.)
- 2020-10-13 10:33:10下载
- 积分：1
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DMA
针对QUARTUS的DMA的VHDL代码实现(DMA Controller Code in VHDL)
- 2009-07-04 23:14:32下载
- 积分：1
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DE2_WEB_QII_60
ALTERA官方板子DE2官方代码，芯片是EP2C35F672C6N(ALTERA official board DE2 official code, the chip is EP2C35F672C6N)
- 2017-09-07 19:35:35下载
- 积分：1
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DE2_115_CAMERA
实现DE2_115开发板上配套的500万像素cmos摄像头捕捉到的画面显示在VGA上(DE2_115 development board supporting 5,000,000 pixels cmos camera to capture the screen display in VGA)
- 2020-07-09 19:08:55下载
- 积分：1
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表决器，简单实现了表决功能，无显示功能
表决器，简单实现了表决功能，无显示功能 -vote
- 2022-05-17 19:43:31下载
- 积分：1
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algorithm_design_and_logic_implemention
本书作者为夏宇文，详细讲解了从算法设计与验证到硬件逻辑实现的过程，要求读者有一定的verilog基础(This book author XIA Yu-Wen gave a detailed account from algorithms to hardware logic design and verification of implementation process, requiring readers to have some basis for verilog)
- 2009-11-11 21:19:03下载
- 积分：1
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verilog编写的流水线模块
verilog编写的流水线模块-Verilog modules prepared by the Pipeline
- 2022-03-30 09:04:46下载
- 积分：1
