-
SPI的VHDL程序，经过quartus验证的，不错！
SPI的VHDL程序，经过quartus验证的，不错！-SPI of the VHDL program, after verification quartus, yes!
- 2022-12-07 04:00:03下载
- 积分：1
-
基于vhdl的dds设计
基于vhdl的dds任意函数发生器的实现和仿真
- 2022-12-25 16:15:09下载
- 积分：1
-
Verilog 编写的ISP1362的控制器IP核，altera公司DE2系统中的源程序
Verilog 编写的ISP1362的控制器IP核，altera公司DE2系统中的源程序-Verilog prepared ISP1362 controller IP core, altera company source DE2 System
- 2022-07-27 16:33:17下载
- 积分：1
-
interr_timer0
interruption routine for PIC16F877
- 2009-12-30 00:43:05下载
- 积分：1
-
des加密算法的verilog语言的实现
des加密算法的verilog语言的实现-des encryption algorithm to achieve the Verilog language
- 2023-09-07 20:45:02下载
- 积分：1
-
091655
基于fpga的coms摄像头
扫描，参考文献，(Fpga based on the coms camera scan, reference literature,)
- 2010-08-09 01:03:12下载
- 积分：1
-
计数器的VHDL代码
这是VHDL中计数器的代码。
- 2022-07-14 16:48:21下载
- 积分：1
-
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0],...
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
- 2022-06-13 02:00:08下载
- 积分：1
-
数字频率计
说明： 设计一简易数字频率计，其基本要求是：
1)测量频率范围0～999999Hz；
2)最大读数999999HZ,闸门信号的采样时间为1s；.
3)被测信号可以是正弦波、三角波和方波；
4)显示方式为6位十进制数显示；
5）具有超过量程报警功能。
5)输入信号最大幅值可扩展。
6）测量误差小于+-0.1%。
7)完成全部设计后，可使用EWB进行仿真，检测试验设计电路的正确性。(The basic requirements of designing a simple digital frequency meter are:
1) The measuring frequency range is 0-999999 Hz.
2) The maximum reading is 999999HZ, and the sampling time of gate signal is 1 s.
3) The measured signal can be sine wave, triangle wave and square wave.
4) The display mode is 6-bit decimal number display.
5) It has alarm function beyond range.
5) The maximum amplitude of input signal can be expanded.
6) The measurement error is less than +0.1%.
7) After completing all the design, EWB can be used to simulate and test the correctness of the circuit.)
- 2019-06-20 12:47:51下载
- 积分：1
-
这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!...
这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!-This is my learning process in the middle of the 10-minute program, containing various clock module and the counter, accumulator, and can download, compile!
- 2022-07-19 00:32:21下载
- 积分：1
