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PCIe_Lab(ALTERA-V5PCIe)
这一设计实例深入浅出，介绍怎样产生一个Qsys子系统。 您将产生一个含有以下组成的Qsys系统:在Cyclone IV GX收发器入门套件上,设计带嵌入式收发器的Gen1×1硬核IP的 PCI Express IP编译器。
(Qsys system: the Cyclone IV GX Transceiver Starter Kit, designed with embedded transceivers Gen1 × 1 hard IP PCI Express IP compiler.)
- 2020-12-02 18:39:25下载
- 积分：1
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CICFilter
文章运用分级抽取和多相滤波的方法改进传统CIC滤波器的结构,降低了系统工作频率,运用幅度改进函数(ACF)和外加级联余弦预滤波器的技术改进了滤波器频率响应,提出了一种高效的算法结构,改善了通带损耗,增大了阻带衰减,对CIC滤波器的实际应用和深入研究有着现实意义。
(Article the use of hierarchical multi-phase extraction and filtering methods to improve the structure of the traditional CIC filter, reducing the system operating frequency, the use of margin to improve the function (ACF) and the cosine cascade plus pre-filter technology to improve the filter frequency response, the an efficient algorithm to improve the pass-band loss, increases the stopband attenuation of the CIC filter in practical applications and in-depth study has practical significance.)
- 2020-08-14 11:08:27下载
- 积分：1
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McBSP_8bit_Asyn
基于FPGA的Mcbsp通信源码，经过项目实测检验(Mcbsp communication source code based on FPGA,Through the test of the project.)
- 2018-03-19 17:19:17下载
- 积分：1
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yiweijicunq
说明： 16位右移位寄存器
下面描述的是一个位宽为16位的右移位寄存器，实际具有环形移位的功能，是在右移位寄存器的基础上将最低位的输出端接到最高位的输入端构成的。其功能为当时钟上升沿到达时，输入信号的最低位移位到最高位，其余各位依次向右移动一位。(16-bit right shift register
The following description is a right shift register with a bit width of 16 bits. It actually has the function of circular shift. It is based on the right shift register, which connects the lowest bit output terminal to the highest bit input terminal. Its function is that when the rising edge of the clock arrives, the lowest displacement of the input signal reaches the highest position, and the rest of you move one bit to the right in turn.)
- 2020-08-18 09:58:21下载
- 积分：1
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Gap_Finder
this example finds the gapes that are existed in a word
- 2010-01-29 18:41:25下载
- 积分：1
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TMDXEVM6678L_EVM_A101-1_GBR
TMS320C6678 EVM TMS320C6678 EVM GOOD(TMS320C6678 EVM GOOD TMS320C6678 EVM GOOD)
- 2013-08-15 08:50:26下载
- 积分：1
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MATLABABCv2
The aim of the ECG simulator is to produce the typical ECG waveforms of different leads and as many arrhythmias as possible. My ECG simulator is a matlab based simulator and is able to produce normal lead II ECG waveform.
- 2017-08-21 21:31:42下载
- 积分：1
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blocking
基于verilog语言的数据选择器，包括数据选择器的测试模块
(verilog language based on the data selector, including data selection for the test module)
- 2007-03-22 09:05:10下载
- 积分：1
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用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core....
用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.-algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company"s paid Multiplier ip core.
- 2022-03-30 14:40:42下载
- 积分：1
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FPGA_merge
关于FPGA排序算法的研究文献，有全排序和一些归并算法的文献介绍。(FPGA sequencing algorithm on the literature, there are some sort of sorting algorithm and the literature on the merger.)
- 2016-11-22 21:12:56下载
- 积分：1
